Prototype of Massively Parallel Electron Beam Write (MPEBW) system was developed for mask less lithography. A 100×100 array of nanocrystalline-silicon (nc-Si) electron emitter is controlled by an active matrix driving LSI. The LSI receives external writing bitmap data, and switches 100×100 electron beamlets on/off. The operation of the LSI was confirmed and 1/100 reduction electron optic system using the active matrix emitter array was fabricated. A 17×17 nc-Si emitter array was assembled with a 1:1 exposure test system and driven by commercially available display driver LSIs. The active matrix electron beam (EB) exposure was confirmed.
In this study, a simulation analysis of a miniaturized electron optics for the Multi-Column Massively Parallel Electron Beam Writing system is demonstrated. Analytical evaluation of space charge effect with prototype Massively Parallel Electron Beam Writing (MPEBW) system showed 2.86 nm blur in radius occurs on each beam with a convergence half angle of 3 mrad. The angle of each beam was increased to 10 mrad to reduce the space charge effect, the coulomb blur amount can be kept to less than 1 nm in radius. However, there was limitation to increasing the angle due to a spherical aberration. Since the beam current density from the electron emitter array in the prototype MPEBW system was 100 μA/cm2 and the total beam current was 1μA with 100×100 array of 10μm square emitter, the influence of coulomb blur was small. By contrast, considerably increasing the number of beams and the beam current are planned in near future in MPEBW. The coulomb blur and other aberrations will not be controlled by merely adjusting the beam convergence angle. In order to increase total beam current, miniaturized electron optics have been designed for Multi-beam+Multi-column system. Reduction lens in the designed miniaturized electron optics with crossover free to reduce the influence of coulomb repulsion with narrow convergence half angle. Unlike conventional methods, the electron beams as principal rays do not intersect at one point, so even if the beam becomes extremely narrow, the coulomb repulsion effect does not increase at the crossover area. The reduction of the entire size of parallel beams in the designed electron optics was confirmed by simulation software. The simulation results showed that least confusion disk of 6.5 nm size was obtained at the beam convergence half angles of 3 mrad corresponding to the incident beam of ±0.1 mrad divergence angle. It showed that the miniaturized electron optics was suitable for 10 nm order EB writing. The crossover free electron optics of the miniaturized electron optics is possible due to dispersing the intersection points of the principal rays by a combination of a concentric electron optics and a tapered lens electrode of the reduction lens.
Developments of a Micro Electro-Mechanical System (MEMS) electrostatic Condenser Lens Array (CLA) for a Massively Parallel Electron Beam Direct Write (MPEBDW) lithography system are described. The CLA converges parallel electron beams for fine patterning. The structure of the CLA was designed on a basis of analysis by a finite element method (FEM) simulation. The lens was fabricated with precise machining and assembled with a nanocrystalline silicon (nc-Si) electron emitter array as an electron source of MPEBDW. The nc-Si electron emitter has the advantage that a vertical-emitted surface electron beam can be obtained without any extractor electrodes. FEM simulation of electron optics characteristics showed that the size of the electron beam emitted from the electron emitter was reduced to 15% by a radial direction, and the divergence angle is reduced to 1/18.
Making the best use of the characteristic features in nanocrystalline Si (nc-Si) ballistic hot electron source, an alternative lithographic technology is presented based on two approaches: physical excitation in vacuum and chemical reduction in solutions. The nc-Si cold cathode is composed of a thin metal film, an nc-Si layer, an n+-Si substrate, and an ohmic back contact. Under a biased condition, energetic electrons are uniformly and directionally emitted through the thin surface electrodes. In vacuum, this emitter is available for active-matrix drive massive parallel lithography. Arrayed 100×100 emitters (each emitting area: 10×10 μm2) are fabricated on a silicon substrate by a conventional planar process, and then every emitter is bonded with the integrated driver using through-silicon-via interconnect technology. Another application is the use of this emitter as an active electrode supplying highly reducing electrons into solutions. A very small amount of metal-salt solutions is dripped onto the nc-Si emitter surface, and the emitter is driven without using any counter electrodes. After the emitter operation, thin metal and elemental semiconductors (Si and Ge) films are uniformly deposited on the emitting surface. Spectroscopic surface and compositional analyses indicate that there are no significant contaminations in deposited thin films.
N. Koshida, A. Kojima, N. Ikegami, R. Suda, M. Yagi, J. Shirakashi, T. Yoshida, Hiroshi Miyaguchi, Masanori Muroyama, H. Nishino, S. Yoshida, M. Sugata, Kentaro Totsu, M. Esashi
Making the best use of the characteristic features in nanocrystalline Si (nc-Si) ballistic hot electron source, the alternative lithographic technology is presented based on the two approaches: physical excitation in vacuum and chemical reduction in solutions. The nc-Si cold cathode is a kind of metal-insulator-semiconductor (MIS) diode, composed of a thin metal film, an nc-Si layer, an n+-Si substrate, and an ohmic back contact. Under a biased condition, energetic electrons are uniformly and directionally emitted through the thin surface electrodes. In vacuum, this emitter is available for active-matrix drive massive parallel lithography. Arrayed 100×100 emitters (each size: 10×10 μm2, pitch: 100 μm) are fabricated on silicon substrate by conventional planar process, and then every emitter is bonded with integrated complementary metal-oxide-semiconductor (CMOS) driver using through-silicon-via (TSV) interconnect technology. Electron multi-beams emitted from selected devices are focused by a micro-electro-mechanical system (MEMS) condenser lens array and introduced into an accelerating system with a demagnification factor of 100. The electron accelerating voltage is 5 kV. The designed size of each beam landing on the target is 10×10 nm2 in square. Here we discuss the fabrication process of the emitter array with TSV holes, implementation of integrated ctive-matrix driver circuit, the bonding of these components, the construction of electron optics, and the overall operation in the exposure system including the correction of possible aberrations. The experimental results of this mask-less parallel pattern transfer are shown in terms of simple 1:1 projection and parallel lithography under an active-matrix drive scheme.
Another application is the use of this emitter as an active electrode supplying highly reducing electrons into solutions. A very small amount of metal-salt solutions is dripped onto the nc-Si emitter surface, and the emitter is driven without using any counter electrodes. After the emitter operation, thin metal (Cu, Ni, Co, and so on) and elemental semiconductors (Si and Ge) films are uniformly deposited on the emitting surface. Spectroscopic surface and compositional analyses indicate that there are no significant contaminations in deposited thin films. The implication is that ballistic hot electrons injected into solutions with appropriate kinetic energies induce preferential reduction of positive ions in solutions with no by-products followed by atom migration, nuclei formation, and the subsequent thin film growth. The availability of this technique for depositing thin SiGe films is also demonstrated by using a mixture solution. When patterned fine emission windows are formed on the emitter surface, metal and semiconductor wires array are directly deposited in parallel.
The characteristics of a prototype massively parallel electron beam direct writing (MPEBDW) system are demonstrated. The electron optics consist of an emitter array, a micro-electro-mechanical system (MEMS) condenser lens array, auxiliary lenses, a stigmator, three-stage deflectors to align and scan the parallel beams, and an objective lens acting as a reduction lens. The emitter array produces 10000 programmable 10 μm square beams. The electron emitter is a nanocrystalline silicon (nc-Si) ballistic electron emitter array integrated with an active matrix driver LSI for high-speed emission current control. Because the LSI also has a field curvature correction function, the system can use a large electron emitter array. In this system, beams that are incident on the outside of the paraxial region of the reduction lens can also be used through use of the optical aberration correction functions. The exposure pattern is stored in the active matrix LSI’s memory. Alignment between the emitter array and the condenser lens array is performed by moving the emitter stage that slides along the x- and y-axes, and rotates around the z-theta axis. The electrons of all beams are accelerated, and pass through the anode array. The stigmator and the two-stage deflectors perform fine adjustments to the beam positions. The other deflector simultaneously scans all parallel beams to synchronize the moving target stage. Exposure is carried out by moving the target stage that holds the wafer. The reduction lens focuses all beams on the target wafer surface, and the electron optics of the column reduces the electron image to 0.1% of its original size.
This study demonstrated our prototyped Micro Electro Mechanical System (MEMS) electron emitter
which is a nc-Si (nanocrystalline silicon) ballistic electron emitter array integrated with an active-matrix driving
LSI for high-speed Massively Parallel Electron Beam Direct Writing (MPEBDW) system. The MPEBDW
system consists of the multi-column, and each column provides multi-beam. Each column consists of emitter
array, a MEMS condenser lens array, an MEMS anode array, a stigmator, three-stage deflectors to align and to
scan the multi beams, and a reduction lens as an objective lens. The emitter array generates 100x100 electron
beams with binary patterns. The pattern exposed on a target is stored in one of the duplicate memories in the
active matrix LSI. After the emission, each electron beam is condensed into narrow beam in parallel to the axis
of electron optics of the system with the condenser lens array. The electrons of the beams are accelerated and
pass through the anode array. The stigmator and deflectors make fine adjustments to the position of the beams.
The reduction lens in the final stage focuses all parallel beams on the surface of the target wafer. The lens
reduces the electron image to 1%-10% in size.
Electron source in this system is nc-Si ballistic surface electron emitter. The characteristics of the
emitter of 1:1 projection of e-beam have been demonstrated in our previous work. We developed a Crestec
Surface Electron emission Lithography (CSEL) for mass production of semiconductor devices. CSEL system is
1:1 electron projection lithography using surface electron emitter. In first report, we confirmed that a test bench
of CSEL resolved below 30 nm pattern over 0.2 um square area. Practical resolution of the system is limited by
the chromatic aberration. We also demonstrated the CSEL system exposed deep sub-micron pattern over
full-field for practical use.
As an interim report of our development of MPEBDW system, we evaluated characteristics of the
emitter array integrated with an active-matrix driving LSI on the CSEL system in this study. The results of its
performance as an electron source for massively parallel operation are described. The CSEL as an experimental
set consisted of the emitter array and a stage as a collector electrode that is parallel to the surface of the emitters.
An accelerating voltage of about -5 kV was applied to the surface of the emitter array with respect to the
collector. The target wafer and the emitter array were set between two magnets. The two magnets generated
vertical magnetic field of 0.5 T to the surface of the target wafer. A gap between the emitter array and the target
wafer was adjusted to a focus length depending on electron trajectories in the electromagnetic field in the system.
The emitter array projected 100x100 electron beams with binary patterns and a dots image of its original size on
the target wafer. The certain array was examined in order to evaluate the property of the e-beam exposure.
We present a prototype electron emitter array integrated with an active-matrix driving large-scale integrated circuit (LSI) for a high-speed massively parallel direct-write electron-beam (e-beam) system. In addition, we describe the results of a performance evaluation of it as an electron source for massively parallel operations. The electron source is a nanocrystalline Si (nc-Si) ballistic surface electron emitter in which a 1∶1 projection of the e-beam can resolve patterns 30 nm wide. The electron-emitting part of the device consists of an array of nc-Si dots fabricated on an SOI or Si substrate and through silicon via (TSV) plugs connected to the dots from the back of the substrate. The device consists of an aligned joint of TSV plugs with driving pads on the active-matrix LSI. Electron emissions are driven by the LSI and are boosted to an appropriate level using a built-in voltage level shifter in accordance with a bitmap image preliminarily stored in the embedded memory. Electron emissions from a test array work as intended, showing the possibility of switching on and off the beamlets by changing the CMOS-compatible voltage.
This paper presents our designed and prototyped structure of electron emitter array integrated with an active-matrix
driving LSI for high-speed massively parallel direct-write electron-beam (e-beam) system. In addition, the validation
results of its performance as an electron source for massively parallel operation are described. Electron source used in
this system is nanocrystalline Si (nc-Si) ballistic surface electron emitter where 1:1 projection of e-beam has been
demonstrated to resolve patterns of 30 nm in width in our previous work. Electron emitting part of the device consists of
arrayed dots of nc-Si emitter fabricated on SOI or Si substrate, and TSV (Through Silicon Via) plugs connected to the
dots from back side of the substrate. Forming an aligned joint of the TSV plugs with driving pads on the active-matrix
LSI constitutes the device. Electron emission is driven by the LSI operation, boosted up to appropriate level by the builtin
voltage level shifter, in accordance with a bitmap image preliminarily stored in an embedded memory. Electron
emission from a test structure of arrayed dot patterns of nc-Si emitter worked in practice, showing the possibility to
switch on and off the beamlets by changing CMOS-compatible voltage.
We have developed a Crestec Surface Electron emission Lithography (CSEL) for mass production of
semiconductor devices. CSEL system is 1:1 electron projection lithography using surface electron emitter. In
first report, we confirmed that a test bench of CSEL resolved below 30 nm pattern over 0.2 um square area.
Practical resolution of the system is limited by the chromatic aberration. We improved the resolution of the
prototype CSEL system by reducing the initial energy spread of electrons and/or by increasing the electric field
intensity. An energy spread of emitted electrons of a nanosilicon planar ballistic electron emitter (PBE) is very
small. After that, the prototype CSEL system exposed sub-micron patterns distributed over 3 mm square area in
last report.
In this study, we examine the prototype CSEL system exposed deep sub-micron pattern over full-field for
practical use. The experimental column of the system is composed of the PBE and a stage as a collector
electrode that is parallel to the electron source. An accelerating voltage of about -5 kV is applied to the electron
source with respect to the collector. The target wafer and PBE are set between two magnets. The two magnets
generate vertical magnetic field of 0.5 T to the surface of the target wafer. A gap between the electron source
and the target wafer is adjusted to a focus length depending on electron trajectories in the electromagnetic field
in the system. The electron source projects a patterned electron image on the target since the patterned mask was
formed on the surface electrode of the electron source. The electrons are emitted from openings of the mask.
When a pulsed bias voltage is applied to the electron source, the electron source emits a patterned surface
electron beam. The beam strikes the resist film coated on the target wafer and make replica of the pattern. We
indicate the system exposes line patterns of about 200 nm in width over large area. An advantage of CSEL is
high resolution due to small chromatic aberration, and another advantage is potentially high throughput because
the coulomb blur is small without any crossover in the electron optics. When we get sufficient current from the
electron source the throughput can be more than 100 wafers/hour.
In this paper we report on the development of a Surface Electron Emission Lithography system (SEL) for high resolution
and high throughput Electron Beam (EB) lithography. The Parallel EB lithography is performed on a 1:1 prototype electron
stepper. A planar type silicon nanowire array ballistic electron emitter (PBE) is employed as a patterned electron emitting
mask in this system.
The PBE has a metal / silicon nanowire array / semiconductor structure. The nanowire is composed of interconnected
silicon nanocrystallites. When a bias voltage is applied to the nanowire, the electrons injected from semiconductor substrate
are accelerated via cascade tunneling between silicon nanocrystallites, and emitted from metal surface electrode. The PBE
exhibits properties originated from the ballistic transport in nanosilicon layer. The electrons are emitted with uniform
intensity in the surface. The emission current is fluctuation-free and low sensitivity against an environmental atomosphere.
The PBE projects the pattern on the target wafer in the electron optics of parallel electric and magnetic fields. If all emitted
electrons have same initial velocity, they are focused at the same distance. The pattern of the mask on the PBE is reproduced
on the target wafer at the distance of the n (n=1, 2, ...) cycle of the spiral trajectory of the electron. Practical resolution is
limited by the chromatic aberration in this system. We can improve the resolution by reducing the initial energy spread and
emission angle dispersion of the emitted electrons because of the characteristics of the ballistic electron emission from PBE.
In this study, we confirmed that the submicron patterns is reproduced all over the area of 2.8 mm square. This
homogeneity of exposure in the extended area results from the uniformity of nanowire array produced by self-organized chemical reaction process. This technique will be available to produce next generation MEMS with lower cost than that of optical stepper.
Sub-30 nm resolution parallel EB lithography based on a planar type silicon nanowire array ballistic electron emitter
(PBE) is demonstrated in this paper. The Parallel EB lithography is performed on a 1:1 electron projection system. The
system consists of the PBE as a surface electron source, a target wafer parallel to the electron source, and uniform
vertical electromagnetic fields. The PBE contained the desired pattern and projected the patterned electron image on the
target. Using the PBE, the electron projection system provides a high resolution of the parallel lithography without any
serious chromatic aberrations. The PBE emits ballistic and/or quasiballistic electrons with small angle dispersion and
small energy dispersion by quantum confinement effect in the PBE. As results of that, the parallel EB lithography
achieved high resolution below 30nm even in a low accelerating voltage condition. The 1:1 paralell EB lithography
system based on the PBE provides next generation device fabrication technique.
As the scaling of single-crystalline silicon (c-Si) size comes into the region below 4 nm
corresponding to the Bohr radius of exciton in c-Si, the original optical, electrical, thermal, and chemical properties of c-Si are substantially modified due to the occurrence of quantum confinement effect. As a consequence, some useful functions are induced in various manners. Nanoporous silicon (PS), composed of highly packed quantum-sized nanosilicon dots, is regarded as a typical quantum silicon material. This paper summarizes various physical effects induced in PS: bannd gap widening, complete carrier depletion, surface activity, and so on. To indicate their technological potential, the present status of application studies is addressed in terms of visible electroluminescent device, components for photonic integration, field-induced ballistic electron emitter, thermally induced ultrasonic emitter, and biocompatible scaffold. Further technological potential is discussed from viewpoints of exploring functional integration.
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