Etching process is an indispensable patterning step in semiconductor device manufacturing. The etch bias compensation is critical in optical proximity correction (OPC) to ensure lithography fidelity and device performance. Therefore, accurate prediction of etch bias has become more crucial as moving to advanced technology node etching process. This study aims to develop an etch bias prediction model based on ensemble learning, specifically utilizing the Random Forest algorithm. A substantial simulation results comprising linewidth, pitch, and corresponding etch bias data for one-dimensional layouts was collected. Subsequently, we employed the Random Forest algorithm, a powerful ensemble learning method, to construct the etch bias prediction model. Random Forest effectively captures the intricate relationships between linewidth, pitch, and etch bias by combining multiple decision trees. Finally, we utilized transfer learning techniques to fine-tune a pre-trained random forest model using real experimental data, resulting in the final model. Compared to traditional machine learning methods, such as the BP neural network, this approach features with faster training speed and better robustness, the Random Forest model exhibits stronger transferability across different technology nodes and different process conditions.
Atomic layer deposition (ALD) technology is a self-limiting film deposition process that grows films on substrates through repeated process cycles of precursor dosing, purge, co-reactant dosing and purge. This technology is widely utilized in advanced technology node processes due to its merits of excellent step coverage and atomic scale film thickness control. However, as the industry moves to three-dimensional (3D) device architectures, ALD faces emerging challenges such as the bottle neck phenomenon in extremely high aspect ratio structure with nanometer scale trench or hole open. ALD modeling provides insights into the underlying mechanisms and help engineers optimize the process. There has been research on different kind of ALD process models on film conformity, growth profile and saturation behavior at multiscale from reactor to micro-feature and molecular level. Angel Yanguas-Gil et al. proposed a reactor scale model which discussed the ideal and non-ideal self-limited processes in a cylindrical and a 300 mm wafer cross-flow reactor. Adomaitis et al. presented a multiscale model to describe the reactant transport in a high aspect ratio nanopore and growth of ALD film based on continuum and Monte Carlo model. In this work, we propose an ALD model in order to simulate the spatial ALD process, coupling with surface reaction kinetics theory and hydrodynamics model. Firstly, we analyze and model the adsorption process of precursor molecules and co-reactant molecules, as well as their transport mechanism in ALD reactor chamber. Secondly, we discuss how the substrate temperature, precursor and co-reactant partial pressure, and reaction probabilities influence coverage distribution and growth per cycle in spatial ALD process. This model enables the possibility of spatial ALD process parameter optimization in an efficient and economy way.
Bowing is one of plasma etching effects that negatively impact device performance. Although there has been plenty of research work on micro-feature surface etch modeling to investigate bowing effect, limited research has been reported on the influence of hardmask morphology on bowing effect. In this paper, we present a plasma etching model based on Monte Carlo simulation with cellular method in order to simulate the feature profile evolution of etching process in nano-scale. The relationship among hardmask angle, open CD and distribution of reflected ion flux on the sidewall from the opposite hardmask was calculated. The reflected ion flux was heavily concentrated in the upper part of the sidewall in the case of a tapered hardmask, and this was the main mechanism of the bowing formation. This model considers chemical reactions and a novel particle reflection algorithm which is a prominent mechanism. This model is capable of reproducing the feature in periodic dense trenches with dimension of tens of nanometers. The hardmask morphology considered in our study includes hardmask angle (θ) and pattern (CD and pitch). As the hardmask angle decreases, the bowing becomes severe, when CD equals to 90nm and θ equals to 70°, the bowing deviation (D=(W-CD)/2) and relative deviation (Δ D=D/CD×100 %) are 23.86nm (26.51 %). In contrast, as the CD increases, the bowing becomes slight. However, bowing moves toward the bottom of the hole as the CD increases. When CD equals to 150nm and θ equals to 70°, the bowing deviation is 18.95nm (12.63 %). Accordingly, a vertical hardmask is very important for a small CD trench.
Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH4/NH3/N2. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager fneu value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.
The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.
In gate-all-around nanosheet (GAA-NS) transistor manufacturing, the SiGe layer plays an important role as a sacrificial layer, requiring precisely controlled and highly selective isotropic etching. In our previous work, we proposed a novel isotropic selective quasi-atomic layer etching (quasi-ALE) method based on O2 plasma self-limiting oxidation and CF4/C4F8 self-limiting selective etching. A vertical nanowire transistor with a diameter less than 20nm and an accuracy error less than 0.3nm has been developed. In this paper, we adopt this method to cavity etching of horizontally stacked nanosheets, using an ICP source to perform self-limiting oxidation of the SiGe layer followed by self-limiting selective removal of oxide (a two-step self-limiting cycle) to form inner spacer cavity. Experimental results show that compared with the strong dependence of the etching amount on SiGe thickness and Ge composition in traditional ICP dry etching, the quasi-ALE technology tends to weaken this size and concentration loading effect due to the self-limiting of each cycle reaction. In addition, we also demonstrated the latest progress in corresponding ALE simulation using a commercial feature-scale plasma process simulator named PEGASUS. The simulation results show that the SiGe etching amount per cycle (EPC) is about 0.3nm, which is basically consistent with the experimental results. This quasi-ALE method demonstrates promising performance for preparing GAA device channels, nanosensors, and other application in future.
Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm
technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer
formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of
SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires
precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In
our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the
results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching
performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with
mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We
reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is
capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern
pitch and stack layer thickness on lateral etch results have been studied by simulation.
KEYWORDS: Plasma enhanced chemical vapor deposition, Low pressure chemical vapor deposition, Silicon nitride, Chemical vapor deposition, Nanosheets, Monte Carlo methods, Particles, Modeling, Transistors, Solids
Gate-all-around nanosheet (GAA-NS) transistors are commonly considered to be most competitive logic device in the future. In the GAA nanosheet transistor device fabrication process, the inner spacer formation is a critical step as it physically isolates the gate from the source/drain, and defines the gate length. After the selective lateral etch of the SiGe in alternative Si/SiGe stack, inner spacer material is deposited and SiNx is commonly used. This gap filling process demands for highly uniform growth of materials in order to minimize transistor variability. As moving to three-dimensional stacked structure, lateral open features bring challenges to conventional deposition manners such as chemical vapor deposition (CVD). In our previous work, we have compared the filling performance between low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), and demonstrated good SiNx growth conformity by LPCVD in Si/SiGe indentation cavities. The cavity geometry was also found to pose significant impact on growth profile. However these works were carried out on isolated Si/SiGe nanosheet structure without neighboring unit. CVD process performance may degrade when moving from isolated to dense structures, especially when the critical dimension goes into tens of nanometers. In this paper, we present our latest simulation progress on the profile evolution of SiNx CVD in dense Si/SiGe nanosheet structures with varying geometry and density of units. The SiNx profile simulation indicates that LPCVD still maintains promising coverage performance in cavities, the SiNx film thickness in the inner and outer side of unit are pretty close, while necking signature emerges near the unit top as process time increases. In contrast, PECVD exhibits pin holes within the cavity at the beginning of process, and the necking effect is relatively severe both in the cavity and near top of unit. We conduct systematic study on periodic stack structure array with different SiGe indentations. Pin holes are observed and get more pronounced in the PECVD process when the space between units is narrowed down. As the indentation decreases, pin holes become much smaller and exhibit better filling performance inside the lateral cavity.
KEYWORDS: Low pressure chemical vapor deposition, Plasma enhanced chemical vapor deposition, Scanning electron microscopy, Silicon, Ions, Field effect transistors, Transmission electron microscopy, Process modeling, Deposition processes, Computer simulations
The inner spacer process is a critical step in gate-all-around (GAA) nanosheet FET device fabrication and SiN is the most common material to be deposited after the indentation of the SiGe layer of alternative Si/SiGe layer structure. This gap filling process demands for highly uniform growth in order to minimize transistor variability, the lateral open feature of the indentation brings new challenges to conventional deposition technologies such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). In this work, we propose an analytical model of SiN deposition to predict the profile evolution of both LPCVD and PECVD, which can help process tuning and understand the influence of the multi-layer geometry and process condition on inner spacer growth performance in a more efficient and economical way. Experimental results reveal that the filling effect of LPCVD is significantly better than that of PECVD, simulation results also validate this. We also compare simulations with experiments, by comparing the model output with original SEM image, satisfactory matching between the two profiles demonstrates the validity of this model. Moreover, we set the SiGe layer thickness to be 10nm, 20nm and 30nm, and SiGe indentation as 10nm, 30nm and 50nm. Simulation reveals that the geometry has significant impact on the deposition performance. When the indentation is less than 10nm, both LPCVD and PECVD exhibit good SiN coverage. However, when indentation is deepened from 10nm to 30nm and 50nm, for PECVD, void firstly forms in 10nm thick SiGe layer and the necking effect tends to form larger void in 20nm and 30nm thick SiGe layers. For LPCVD, however, SiN grows more uniformly within and outside the cavity, and only very narrow gaps form in the cavity.
Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD.
Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level.
Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout.
Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%.
Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology.
As the semiconductor manufacturing critical dimension continues to shrink, the requirement placed on overlay control becomes much more stringent. Due to the fact that the absolute overlay tolerances are approaching 2-3 nm, process induced errors can be a major contribution to the overlay error. For instance, chemical mechanical polishing (CMP) are found to cause 1-3 nm overlay measurement error, which is of the same magnitude to the total overly budget. Because of this, efforts are being made to investigate the mechanism of overlay shift caused by process variations. In this paper, we present a study of the Diffraction based Overlay (DBO) metrology with a model based on the Finite-Difference Time-Domain (FDTD) method on the impact of CMP process to overlay measurement. Measurement error caused by CMP are discussed. Our investigation shows that the impact of the CMP process can cause the +/- diffraction orders to become asymmetric, which will confuse DBO measurement signals. This study has been performed across the visible illumination spectrum and the result of our study will be illustrated.
It is possible to achieve mass production by multiple patterning technology combing with 193 immersion scanners at 7nm technology node. The application of freeform illumination source shapes is a key enabler for continued shrink using 193 nm immersion lithography with 1.35 NA. Source and mask optimization (SMO) is the important resolution enhancement technique (RET) to optimize a satisfied freeform source. Design pattern library can be used to cognize, manage and compare all the continuous changing and iterative physical designs. Our proposed methodology can improve SMO performance by taking advantages of post-color design pattern library and pattern selection method. And process window limiters are the important guidance to optimize parameters of SMO.
Optical proximity correction (OPC) is regarded as one of the most important computational lithography approaches to improve the imaging performance of sub-wavelength lithography process. Traditional OPC methods are computationally intensive to pre-warp the mask pattern based on inverse optimization models. This paper develops a new kind of pixelated OPC method based on an emerging machine learning technique namely graph convolutional network (GCN) to improve the computational efficiency. In the proposed method, the target layout is raster-scanned into pixelated image, and the GCN is used to predict its corresponding OPC solution pixel by pixel. For each layout pixel, we first sub-sample its surrounding geometrical features using an incremental concentric circle sampling method. Then, these sampling points are converted into graph signals. Then, the GCN model is established to process the pre-defined graph signals and predict the central pixel within the sampling region on the OPC pattern. After that, the GCN is moved to predict the OPC solution of the next layout pixel. The proposed OPC method is validated and discussed based on a set of simulations, and is compared with traditional OPC methods.
Layout classification is an important task used in lithography simulation approaches, such as source optimization (SO), source-mask joint optimization (SMO) and so on. In order to balance the performance and time consumption of optimization, it is necessary to classify a large number of cut layouts with the same key patterns. This paper proposes a new kind of classification method for lithography layout patterns based on graph convolution network (GCN). GCN is an emerging machine learning approach that achieves impressive performance in processing graph signals with nonEuclidean topology structures. The proposed method first transforms the layout patterns into graph signals, where the sum of several adjacent layout pixels is associated with one graph vertex. Next, the adjacent graph vertices are connected by the graph edges, where the edge weights are determined by the correlations between the vertices. Therefore, the layout geometries can be represented by the function values on the graph vertices and the adjacency matrix. Subsequently, the GCN framework is established based on the graph Fourier transform, where the input is the graph signal of the layout, and the output is its classification label. The network parameters of GCN are trained in a supervised manner. The proposed method is compared to the simple convolutional neural network (CNN) with a few layers and VGG-16 network, respectively. Finally, the features of different methods are discussed in terms of classification accuracy and computational efficiency.
With the development of process technology nodes, hotspot detection has become a critical process in integrated circuit physical design flow. The machine learning-based method has become a competitive candidate for layout hotspot detector with easy training and high speed. Classic methods usually define hotspot detection as a binary classification problem. However, the designer hopes to further divide the hotspot patterns into a series of levels according to their severity to identify and fix these hotspots. In this paper, we designed a multi-classifier based on the convolutional neural network to realize the detection of various levels of hotspot patterns. Unlike classic cross-entropy loss, we proposed a custom loss function to reduce the difference between false predicted levels and corresponding true levels, reducing the adverse effects caused by misclassified samples. Experimental verification results show that our hotspot detector can correctly classify various hotspots levels and has potential advantages for physical designers to fix hotspots.
KEYWORDS: Optical lithography, Immersion lithography, Lithography, Photomasks, Source mask optimization, Manufacturing, Overlay metrology, Data processing, Standards development, Back end of line
In the early stage of technology node definition and process development, design house owns abundant logic patterns resources and is able to offer fab more potential hotspots to do process window check, accelerating design rule qualification, feedback and optimization. A systematic methodology has been put forward to detect potential hotspots categories and modify related design rules with very insufficient process information for fabless side. It is efficient to conduct the study on a small number of patterns which can be treated as the typical of the whole physical design. Hence the physical design can be managed as a library and grouped by specific pattern signature for every layer. Based on the connectivity of source drain layers and local-interconnect layers, via0, under the first metal layer, is adopted litho-etch (LE) x4 on 193i scanner as the lithography solution. The experiment is carried out on the via0 layer. With consideration of minimum size and multiple limitations of other layers in design rule, systematic pattern analysis, fuzzy pattern search for low NILS, high MEEF and large PV bands have been combined to optimize the related design rules.
Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.
In EUV lithography, the short wavelength and residual mirror surface roughness increase the flare levels across the slit. As a key research point, the flares of different exposure fields are carefully discussed by numerical simulation. To ensure the effectiveness and practicability of our simulations, the test patterns are generated according to the general design rules for 7nm technology node. The NILS, process variation band (PVB) and MEEFs from mask optimizations and source mask optimizations (SMO) results are compared. From the comparisons, the constant flare has a greater influence on NILS and PVB than that on MEEF. In contrast, the flare map caused more reduction on the MEEF values.
An EUV source optimization technique using compressive sensing is introduced in this paper. The pixelated source pattern is sparsely represented in a set of certain basis functions. Blue noise sampling method is used to select sampling points around the margins of the target layout for imaging fidelity evaluation. Based on the compressive sensing theory, the EUV SO is formulated as an l1-norm inverse reconstruction problem and solved by the linearized Bregman algorithm. Different types of sparse bases are also experimented in this paper to investigate their impact on the SO results. These bases include the 2D-DCT basis, spatial basis, Zernike basis, and Haar wavelet basis. Simulations show that ℓthe Haar wavelet basis results in the best imaging fidelity among the four types of bases.
Source optimization (SO) is a widely used resolution enhancement technique to improve the imaging performance of optical lithography systems. Recently, a fast pixelated SO method for inverse lithography has been developed based on the theory of compressive sensing (CS). In last several years, CS has explored numerous reconstruction algorithms to solve for inverse problems. These algorithms are critical in attaining good reconstruction quality also aiming at reducing the time complexity. This paper compares different SO methods based on CS algorithms including the linearized Bregman (LB) algorithm, the alternating direction method of multipliers (ADMM), the fast iterative shrinkage-thresholding algorithm (FISTA), the approximate message-passing (AMP), and the gradient projection for sparse reconstruction (GPSR). Benefiting from the strategy of variable splitting and adaptive step size searching, the GPSR method effectively retains the optimization efficiency. Computational experiments also show that the GPSR method can achieve superior or comparable SO performance on average over other methods. It is also shown that the proposed SO methods can be applied to develop a fast source-mask optimization (SMO) method based on the CS framework.
Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.
An optimized source has the ability to improve the process window during lithography in semiconductor manufacturing. Source optimization is always a key technique to improve printing performance. Conventionally, source optimization relies on mathematical–physical model calibration, which is computationally expensive and extremely time-consuming. Machine learning could learn from existing data, construct a prediction model, and speed up the whole process. We propose the first source optimization process based on autoencoder neural networks. The goal of this autoencoder-based process is to increase the speed of the source optimization process with high-quality imaging results. We also make additional technical efforts to improve the performance of our work, including data augmentation and batch normalization. Experimental results demonstrate that our autoencoder-based source optimization achieves about 105 × speed up with 4.67% compromise on depth of focus (DOF), when compared to conventional model-based source optimization method.
Mask three-dimensional effect (M3D) and flare are the critical issues for lithography in advanced technology nodes, especially for the extreme ultraviolet lithography (EUVL). The M3D effect leads to a shrinkage of critical dimension (CD) and the flare causes the unwanted background exposure. To evaluate impact of these two effects on EUVL performances, the process windows (PWs) of various test patterns under nominal condition are firstly simulated. And then an optimal source is selected by comparing PW values. At last, M3D is introduced by considering absorber thickness, and the flare is introduced by adding a constant distribution across the exposure field. All simulations are implemented by employing SLitho, a commercial software from Synopsys. The test patterns in simulations include line space, tip2tip and tip2line patterns, and the gaps of tip2tip and tip2line are 40, 45 and 50nm. The results of simulation show that mask topography will reduce the DOFs of test patterns, and constant flare has almost no effect on the DOFs of many test patterns.
It is of tremendous impact with multilayer defects, which are caused by particles, substrate pits or scratches, in EUV lithography for the high volume manufacturing. Multilayer defects suppress the productivity and utilization rate of the mask blank. In this paper, we did a thorough investigation by conducting imaging simulations on dense and semi-dense patterns including lines and contact holes. The impact of isolated multilayer defects on the imaging of 22nm half-pitch dense line/contact and 33nm half-pitch semi-dense line has been studied, and the CD errors are calculated. The CD error, caused by the planar defect which is smoothed out during the multilayer deposition process, is found to be within ±10% of target values. This CD error can be compensated by adjusting the exposure dose or local pattern size. In contrast, the non-planar defect, which is not being smoothed in the multilayer surfaces, would lead to severe damages to the lithography performance.
Mask defectivity is a critical challenge to the high-volume production of extreme ultraviolet lithography (EUVL). In a similar way to the optical proximity correction (OPC), mask absorber pattern optimization could weaken the impact of defect on lithography. In order to compensate the amplitude and phase impact caused by the defects on the EUV mask blank, an advanced evolution strategy based on genetic algorithm (GA) combining with manufacturing rule check (MRC) is proposed to optimize the mask pattern. The influences of various defects on lithography are firstly summarized from mass simulation results, as well a novel method based on GA is proposed to compensate the negative impact by defects. Finally, the advantages of the proposed method in convergence efficiency and robustness are validated through comparing with differential evolution (DE) and original GA with simulations on contact patterns and logic patterns with the lithography simulator Sentaurus Lithography (Slitho).
Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.
Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization.
Use of lithography exposure and metrology tools in production typically results in worse performance than seen on test wafers. Physical design always starts with rough design rule for a new technology node. To evaluate the influence of the inevitable degraded performance on test wafers, our paper put forward a systematic approach to evaluate whether the ability of current process can support the design. The approach utilizes litho-friendly design (LFD) to find the yield killers and conducts pattern classification with pattern matching. Process window discovery (PWD) is used to collect the statistical data to confirm whether the yield killers in LFD simulation will meet the systematic fail on wafer. It is necessary to do mask optimization (MO), source mask optimization (SMO) and design rule optimization (DRO) for the real yield killers. Moreover, design of advanced node may include the patterns inside forbidden pitch range. We do the design rule exploration for metal 2 layer of 14nm technology node and discuss the corresponding solutions for width sensitive zone as well.
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