Photolithography plays a major role in leading-edge semiconductor fabrication. Due to the tighter photolithography specification, leading-edge 1γ (1-gamma) DRAM needs the EUV technology. There is a stringent defectivity requirement to meet critical specifications for photolithography. Any failure mode left undetected leads to yield loss and prevents cycles of learning during the early technology development phase and pilot line manufacturing. Due to tighter pitches and a high aspect ratio etch process, EUV lithography levels are prone to defects such as bridging and toppling. Photolithography Track Equipment leads the way in reducing defectivity using advanced processes and hardware optimization. Traditional bare silicon-based PMON (particle monitor) for critical tools and process monitoring is insufficient for leading-edge photolithography. It is unreliable for monitoring chemical interaction-based defectivity. Enabling Photo track monitoring (PTM) shortened cycles of learning and aided in optimizing the photolithography processes for development and production.
In this paper we show experimental verification of the feasibility of printing pitch 40x70nm hexagonal holes using EUV single patterning. We show that at a local CDU (LCDU) of 2.7nm and an exposure dose of 54 mJ/cm2 a defect rate smaller than 7x10-9 is observed. This result was enabled by optimization of the illumination source and improvements in the resist. Resist selection identified multiple candidates that show a promising LCDU performance and optimization of the processing conditions resulted in improved performance. Experimental validation of the defect performance was done using HMI eP5 on the baseline process. Assessment of the LCDU performance for EUV single expose at pitches beyond 40x70nm, showed promising results.
Enormous advances have been made in recent years to design sub 40nm dense contact hole pattern with local CD uniformity (CDU) that the process can tolerate. Negative tone development process (NTD) on 193nm photoresists has achieved this to a large extent without the requirement of additional processing steps on the patterned layer. With further shrinking of size of the subsequent nodes, the demand to produce smaller patterns with wider process window, low defectivity, and improved CDU is increasing, and reaching beyond what can be achieved through NTD alone. A number of techniques are in practice today to achieve this, most notably, implementation of a collar of Atomic Layer Deposited SiO2 (ALD) on photoresist or substrate. However, in recent years, various material suppliers have also proposed shrink chemistries to achieve this. In this paper, we have provided fundamental characterization of shrink via application of spin-on agents (organic as well as aqueous) on the post-imaged pattern. We have also compared them for their shrink capacity, defect tendency, dry etch capability and ease of implementation in the process flow. In addition, we have provided recommendations on which technique is suitable for a given set of process prerequisites.
Directed self-assembly (DSA) of block copolymers (BCPs) is a promising technology for advanced patterning at future technology nodes, but significant hurdles remain for commercial implementation. While chemoepitaxy processes employing poly(styrene-block-methyl methacrylate) (PS-PMMA) are most widely studied for DSA line/space patterning, graphoepitaxy processes using more strongly segregated “high-X;” block copolymers have recently shown a lot of promise, with lower defectivity and line-width roughness (LWR) than comparative chemoepitaxy processes. This paper reports on some of the design considerations for optimizing line/space patterning with these materials. We have found that brush and block copolymer selection are critical to achieve high quality DSA. For example, brush thickness must be optimized to achieve matching space critical dimensions, and brush surface energy impacts kinetics of assembly. The X parameter of the block copolymer should be optimized to balance LWR, kinetics of assembly, and process window. Glass transition temperature (Tg) of the blocks showed little impact on performance. Overall, parameters of both BCP and brush must be simultaneously optimized to achieve high quality DSA.
Block copolymer directed self-assembly (BCP-DSA) may provide a less costly method of forming sub-38nm pitch line-space patterns relative to proven HVM methods, but DSA needs to provide equivalent or improved defect density and pattern quality to warrant consideration for displacing current HVM methods. This paper evaluates the process constraints of three DSA flows and compares the pattern quality after pattern transfer for each flow at its optimal process conditions to the same pattern created by a proven HVM process flow.
Block co-polymer directed self-assembly (BCP DSA) has become an area of fervent research activity as a potential alternative or adjunct to EUV lithography or self-aligned pitch multiplication strategies. This presentation will evaluate two DSA strategies for patterning line-space arrays at 30nm pitch: graphoepitaxial DSA with surface-parallel cylinder BCPs and chemoepitaxial DSA with surface-normal lamellar BCPs. A comparison of pattern transfer into hard-mask and substrate films will be made by consideration of line and space CDs, line profile of cross-sectional SEM images, and comparison of relative LWR/SWR. The processes will be benchmarked against Micron’s process used in manufacturing its 16nm half-pitch NAND part.
Scanner matching based on CD or patterning contours has been demonstrated in past works. All of these published works require extensive wafer metrology. In contrast, this work extends a previously proposed optical pattern matching method that requires little metrology by adding the component requirements and the procedure for creating an automation flow. In a test case, we matched an ASML XT:1900i using a DOE to an ASML NXT:1950i scanner using FlexRay. The matching was conducted on a 4x nm process test layer as a development vehicle for the 2x nm product nodes. The paper summarizes the before and after matching data and analysis, with future opportunities for improvements suggested.
Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment.
Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The
signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are
changed as the wafers go through various processes and are buried underneath complex film stacks. These processes
and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM
to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical
analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on
SLMs and experimentally verifies results using various structures.
Three resist freezing methods (fluoride plasma, chemical and thermal freezing) were studied for double patterning cross
pattern by printing the second layer directly on top of the first resist layer. Different methods show different challenges:
plasma freezing is very hard to remove footing on both layers; Chemical freezing first layer CD will grow after completion
of second pattern; thermal freezing will change line curvature when the CD is smaller than 50nm, if first layer is wave type
pattern.
As the industry drives to lower k1 imaging we commonly accept the use of higher NA imaging and advanced
illumination conditions. The advent of this technology shift has given rise to very exotic pupil spread functions that
have some areas of high thermal energy density creating new modeling and control challenges. Modern scanners are
equipped with advanced lens manipulators that introduce controlled adjustments of the lens elements to counteract the
lens aberrations existing in the system. However, there are some specific non-correctable aberration modes that are
detrimental to important structures. In this paper, we introduce a methodology for minimizing the impact of aberrations
for specific designs at hand. We employ computational lithography to analyze the design being imaged, and then devise
a lens manipulator control scheme aimed at optimizing the aberration level for the specific design. The optimization
scheme does not minimize the overall aberration, but directs the aberration control to optimize the imaging performance,
such as CD control or process window, for the target design. Through computational lithography, we can identify the
aberration modes that are most detrimental to the design, and also correlations between imaging responses of
independent aberration modes. Then an optimization algorithm is applied to determine how to use the lens manipulators
to drive the aberrations modes to levels that are best for the specified imaging performance metric achievable with the
tool. We show an example where this method is applied to an aggressive memory device imaged with an advanced ArF
scanner. We demonstrate with both simulation and experimental data that this application specific tool optimization
successfully compensated for the thermal induced aberrations dynamically, improving the imaging performance
consistently through the lot.
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has
been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise
wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use
of scanner metrology and design data and minimizes the reliance on wafer CD metrology.
A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology
node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements
and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe
to two other recipes that were obtained from the new, optical model based matching method. In the following sections,
we describe the implementation of both methods, provide their predicted and actual improvements after matching, and
compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations
on the relative merits of each method for a variety of use cases.
Unpolarized light has traditionally been used for photolithography. However, polarized light can improve contrast and
exposure latitudes at high numerical aperture (NA), especially for immersion lithography with an NA > 1.0. As
polarized light passes through a reticle, any birefringence (BR) in the reticle material can cause a change in the
orientation or degree of polarization, reducing the contrast in the final resist image. This paper shows the effects of
reticle BR on dry and immersion imaging for 193nm lithography. The BR magnitude and orientation of the fast axis
were mapped across several unpatterned mask blanks, covering a range of BR from 0 to 10 nm/cm. These reticles were
printed with a series of open areas surrounded by test structures. The BR was measured again on the patterned reticles,
and several locations were selected to cover a range of magnitudes at different orientations of the fast axis. Dry and
immersion imaging were evaluated, looking at BR effects on dense lines and contact structures. Mask error
enhancement factor (MEEF), line edge roughness (LER), and dose and focus latitudes were studied on line/space
patterns. Dose and focus latitudes and 2-D effects were studied on contact patterns. Based upon these results, the effect
of reticle BR on CD is minimal, even for BR values up to 10 nm/cm.
A key issue regarding the introduction of 193nm immersion lithography into production is immersion specific defects. One of these new defect types is the formation of air bubbles in the immersion fluid near or on the resist surface, which can then cause significant local dose variations. One possible mechanism for inducing bubble formation is the introduction of surface topography, such as seen on a typical product wafer, which could then disrupt the immersion fluid flow and entrain air. This brings up the question of what, if any, types of topography we need to be worried about and how do we test all the possible variants that will exist on product wafers. To help address this issue we have created a special topography reticle and wafer set and used them for exposures on a prototype immersion scanner. The wafer set was generated using a first level reticle designed to have an extremely wide range of topography types in a modular and systematically varying format. The wafer fabrication included skews of the trench depths, variation of the surface contact angle by using different topcoats, and optimization of the process flow to enable high contrast defect inspections. The second level reticle used for the immersion exposures was designed to cover the entire topography wafer with dose sensitive grating structures to detect any dose modulation caused by bubbles. In this paper we present the design of these reticles and wafers and the results of the first immersion exposures. Flat, unpatterned wafers were also exposed on the immersion tool in order to provide a basis for comparison. A KLA 2351 inspection tool was used to inspect all the wafers for defects. The initial results of these tests did not show a strong interaction of bubbles with topography.
Most 157nm resist optimization to date has been done with micro-steppers, but there may be significant differences in resist profiles and process windows between micro-steppers and full field scanners. Several resists were evaluated on an ASML MS VII full-field 157nm scanner at IMEC. Focus and exposure latitudes were measured for resist lines using various feature sizes and pitches with different reticle types and illumination conditions. Resist sensitivity to post-expose bake temperature were measured. Delay effects, line-edge roughness, line slimming in a CD SEM, and etch resistance were also evaluated.
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