In recent years, curvilinear mask technology has emerged as a next-generation resolution enhancement method for photomasks, providing optimal margins by maximizing the degree of freedom in pattern design. However, this technology presents challenges in defining the layout design rule limits based solely on geometric information, such as width, space, and corner-to-corner. With the introduction of multi-beam mask writers for curvilinear pattern production, a distinct set of defects that are difficult to pre-detect by conventional mask rule check have occurred, as these cannot be explained by geometry terms alone. In this study, we propose a deep learning-based mask check method, named mask deep check (MDC) for pre-detect defects in inspection. The proposed vector graphics transformer (VGT) uses the state-of-the-art transformer architecture, drawing an analogy between the vertices of curvilinear patterns and words in natural language. We demonstrate improved performance of VGT-based MDC compared to a traditional rule-based approach and a convolutional neural network-based MDC method. Importantly, VGT exhibits robustness in recall, ensuring that defective patterns are not misclassified as normal, thereby preventing missed defects. Moreover, by employing attention maps to visualize VGT results, we gain explainability and reveal that mask defects may arise from issues related to the fabrication of specific designs, rather than being solely attributable to geometric features. VGT-based MDC contributes to a better understanding of the challenges associated with curvilinear mask technology and offers an effective solution for detecting mask defects.
Pattern selection for OPC (Optical Proximity Correction) model calibration is crucial for high-quality OPC results and low edge placement error (EPE) error in semiconductor fabrication. Pattern coverage check is also desired with the value to identify potential anomaly before mask tape out for monitoring and repair. This study evaluates pattern diversity based selection and pattern coverage check for Extreme Ultraviolet (EUV) C/H mask layers. Pattern diversity based selection has the advantage of incorporating information related to lithographic contrast and illumination effects, offering a more nuanced representation of patterns in a lithographic context. Using unsupervised machine learning, we analyze the lithographic pattern representations from sample designs and select out pattern representatives for OPC model. The study concludes pattern selection and coverage check can enhance model prediction performance for the OPC applications.
As semiconductor process technology needs to be advanced, the difficulty of patterning increases and unexpected pattern defects occur. In fact, it is very important to quickly identify and resolve these pattern defects in advance, but there is a limit to measuring all of these pattern defects that occur in wafers. In particular, in order to overcome metrological limitations, it may be best to extract actual potential pattern defects by classifying various types of patterns that actually exist. We measured how to classify weak patterns by sampling them based on previously known weak pattern group libraries, simulation-based weak patterns, and unique patterns. Through this method, engineers can subjectively judge how to find weak patterns, and it can be difficult because there is a possibility that the probability of weak patterns is low depending on the limited measurement capacity. In this paper, unsupervised learning is used to cluster and classify by pattern type based on the various features of pattern. Then, based on reliable wafer data for various classified pattern types, the degree of vulnerability to defect was quantified for each classified cluster to give a ranking for extracting a weak pattern group for each cluster, and the weak pattern was extracted based on this to confirm a high weak pattern detection rate. In addition, it provides effective solutions to extract weak patterns from various databases (DBs) and specifically to give reliability to visualization methods.
In recent years, Curvilinear Mask technology has emerged as a next-generation resolution enhancement method for photomasks, providing optimal margins by maximizing the degree of freedom in pattern design. However, this technology presents challenges in defining layout design rule limit based solely on geometric information rules based solely on geometric information such as width, space, and corner-to-corner. With the introduction of Multi Beam Mask Writers for Curvilinear pattern production, brand-new violations of Mask Rule Check(MRC) have occurred, which cannot be explained by geometry terms alone. In this study we propose a deep learning-based method for detecting MRC violations using the state-of-the-art Transformer architecture, drawing an analogy between the vertices of curvilinear patterns and words in natural language. The proposed MRC binary classifier demonstrates improved performance compared to traditional rule-based MRC and CNN-based MRC methods. Importantly, our method exhibits robustness in recall, ensuring that defective patterns are not misclassified as normal, preventing missed defects. Moreover, by employing attention maps to visualize deep learning results, we gain explainability and reveal that MRC violations may arise from issues related to the fabrication of specific designs, rather than being solely attributable to geometric features. This insight contributes to a better understanding of the challenges associated with Curvilinear Mask technology and offers an effective solution for detecting MRC violations.
Background: Natural physical phenomena occurring at length scales of a few nm produces variation in many aspects of the EUV photoresist relief image: edge roughness, width roughness, feature-tofeature variability, etc. 1,2,3,4. But the most damaging of these variations are stochastic or probabilistic printing failures 5, 6. Stochastic or probabilistic failures are highly random with respect to count and location and occur on wafers at spectra of unknown frequencies. Examples of these are space bridging, line breaking, missing and merging holes. Each has potential to damage or destroy the device, reducing yield 6, 10. Each has potential to damage or destroy the device, reducing yield 6, 10. The phenomena likely originates during exposure where quantized light and matter interact1 . EUV lithography is especially problematic since the uncertainty of energy absorbed by a volume of resist is much greater at 13.5 nm vs. 248 nm and 193 nm. Methods: In this paper, we use highly accelerated rigorous 3D probabilistic computational lithography and inspection to scan an entire EUV advanced node layout, predicting the location, type and probability of stochastic printing failures.
Patterning, a major process in semiconductor manufacturing, aims to transfer the design layout to the wafer. Accordingly, the "process proximity correction" method was developed to overcome the difference in after-cleaninginspected CD (critical dimension) between patterns of similar shapes. However, its physical model is often limited in the predictive performance. Therefore, recent studies have introduced ML (machine learning) technology to supplement model accuracy, but this approach often has an inherent risk of overfitting depending on the type of sampled pattern. In this study, we present a newly invented flow capable of stable etch-process-aware ML modeling by model reconstruction and large amounts of measurement data. The new modeling flow can also be performed within a reasonable runtime through efficient feature extraction. Based on the new model and its related layout targeting platform, intensive improvements were made to CD targeting and spread; for a given layout, in comparison with delicate rule-based modification, the CD targeting accuracy was improved by 4 times and approaches the limit of metrology error.
Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.
This paper presents the application of double exposure alternating phase shift mask (APSM) lithography to the 65nm node gate layer. An integrated approach involving optimization of the layout design rules, APSM synthesis, Optical Proximity Correction (OPC), mask manufacturing process, and wafer patterning process has been employed to scale gate layer critical dimensions from the 90nm node to the 65 nm node with no loss in focus or exposure process window. The paper focuses on some of challenges for achieving a production-worthy APSM solution, including discussions of APSM flow development along with aspects of OPC model calibration, OPC performance, CD control, and OPC validation. Patterning results from the application of APSM to the gate level of a state-of-the-art 65nm node random logic technology are presented.
As a continuation of comparison experiments between EUV inspection and visible inspection of defects on EUVL mask blanks, we report on the result of an experiment where the EUV defect inspection tool is used to perform at-wavelength defect counting over 1 cm2 of EUVL mask blank. Initial EUV inspection found five defects over the scanned area and the subsequent optical scattering inspection was able to detect all of the five defects. Therefore, if there are any defects that are only detectable by EUV inspection, the density is lower than the order of unity per cm2. An upgrade path to substantially increase the overall throughput of the EUV inspection system is also identified in the manuscript.
We report on the comparison of defect printability experimental results with at-wavelength defect inspection and printability modeling at extreme ultraviolet (EUV) wavelengths. Two sets of EUV masks were fabricated with nm- scale substrate defect topographies patterned using a sacrificial layer and dry-etch process, while the absorber pattern was defined using a subtractive metal process. One set of masks employed a silicon dioxide film to produce the programmed defects, whereas the other set used chromium films. Line-, proximity- and point-defects were patterned and had lateral dimensions in the range of 0.2 micrometer X 0.2 micrometer to 8.0 micrometer X 1.5 micrometer on the EUV reticle, and a topography in the range of 8 nm - 45 nm. Substrate defect topographies were measured by atomic force microscopy (AFM) before and after deposition of EUV-reflective Mo/Si multilayers. The programmed defect masks were then characterized using an actinic inspection tool. All EUVL printing experiments were performed using Sandia's 10x- reduction EUV Microstepper, which has a projection optics system with a wavefront error less than 1 nm, and a numerical aperture of 0.088. Defect dimensions and exposure conditions were entered into a defect printability model. In this investigation, we compare the simulation predictions with experimental results.
We present recent experimental results from an actinic (operates at the EUV wavelength) defect inspection system for extreme ultraviolet lithography mask blanks. A method to cross-register and cross-correlate between the actinic inspection system and a commercial visible-light scattering defect inspection system is demonstrated. Thus, random, real defects detected using the visible-light scattering inspection tool can be found and studied by our actinic inspection tool. Several defects with sub-100 nm size (as classified by the visible scattering tool) are found with the actinic inspection tool with a good signal to noise ratio. This result demonstrates the capability of the actinic inspection tool for independent defect counting experiments at a sub-100 nm defect sensitivity level.
We have used picosecond ultrasonics techniques to study the localized surface vibrations in Mo/Si multilayers. Two band- gap modes were simultaneously detected using a new alternating pumps scheme, which has been demonstrated to enhance the signal-to-noise ratio by 10 dB.
Recent experimental results from an actinic EUVL mask blank defect inspection system are presented. Bright-field and dark-field scans from various programmed defect samples are reported. Our results show that the current system can detect defects as small as 0.2 micrometers . Substrate roughness is identified as the limitation to the detection sensitivity. A preliminary defect counting experiment is reported and future improvements for practical defect counting are discussed.
We have used picosecond ultrasonic techniques as a nondestructive detection tool to characterize Mo/Si multilayer reflectors for EUV. The lowest two localized acoustic-phonon surface modes were simultaneously observed in our samples with various d and (Gamma) values. The vibration frequencies of these surface modes depend both on d and (Gamma) , and can be used to extract these two parameters. We mapped the thickness profile of a linearly graded Mo/Si multilayer sample with 2 percent d-variation from the two edges towards the center. The dependence of the vibration frequencies on (Gamma) was also studied theoretically and experimentally, and was found to be separable from the dependence on d.
We report the design and initial experimental results of an actinic inspection system for extreme ultraviolet lithography mask blank defect detection. Initial bright-field and dark- field results demonstrate sensitivity to submicron size phase defects.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.