As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements.
Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.
Source Mask Optimization (SMO) is one of the most important techniques available for extending ArF immersion
lithography1. However, imaging with a small k12 factor (~0.3 or smaller) is very sensitive to errors in the illumination
pupil2. As a result, care must be taken to insure that the source solution from SMO can be produced by the real
illuminator, which is subject to its own imaging constraints. One approach is to include an illuminator simulator in the
SMO loop so that only realizable illumination pupils are considered during optimization. Furthermore, any illumination
pupil predictor used in SMO should operate quickly compared to the imaging simulation if it is to avoid increasing the
computational load.
The practical extendibility of immersion lithography to the 45nm half-pitch is being investigated on a 1.30NA immersion projection microstepper installed at SEMATECH North in Albany, New York. Preliminary implementation of various aperture designs and polarization configurations have been used to demonstrate imaging beyond the 90nm pitch. Optical proximity correction (OPC) and other resolution enhancement technique (RET) strategies coupled with resist stack optimization of dual-layer bottom anti-reflective coating (BARC) systems offer a growing platform of materials and illumination configurations for the 45nm node. In this demonstration of a RET strategy, linear-polarized light is selectively rotated at the coherence aperture to simultaneously image sub-90nm pitch features along the x and y axes within the same field. Scanning electron microscope (SEM) images demonstrate the capability of the immersion micro-exposure tool (iMET) to support dual-orientation imaging with resolution down to the 84nm pitch.
Over the years process development engineers found creative ways to extent the capabilities of existing imaging techniques to enable production of the next technology node. For the 45nm node the immersion technology is being prepared for production, along with other resolutions enhancement techniques such as illuminator polarization. In parallel with the development of these tools, modeling techniques are being developed, which are needed in order to establish the design flows and to set up the Optical Proximity Correction (OPC) and mask data preparation. There is a clear need to validate these models and verify them in an early stage. With the equipment not being available yet, other methods like Maxwell simulators and special test equipment are used for such validations. In this paper initial model verification and validation work is presented of a hyper NA models developed for the 45nm technology node. Models with different illuminator settings are used and compared with Maxwell simulators and experimental measurements obtained with an Exitech MS-193i immersion micro-exposure tool.
Polarization dependent diffraction efficiencies in transmission through gratings on specially designed masks with pitch comparable to the wavelength were measured using an angle-resolved scatterometry apparatus with a 193 nm excimer source. Four masks - two binary, one alternating and one attenuated phase shift mask - were included in the experimental measurements. The validity of models used in present commercially available simulation packages and additional polarization effects were evaluated against the experimental scattering efficiencies.
Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.
The recent development of lithographic resolution enhancement techniques of optical proximity correction (OPC) and phase shift masks (PSM) enable sprinting critical dimension (CD) features that are significantly smaller than the exposure wavelength. In this paper, we present a variable threshold OPC model that describes how a pattern configuration transfers to the wafer after resist and etch processes. This 0.18 micrometers CMOS technology utilizes isolation with pitches of active device regions below 0.5 micrometers . The effective gate length on silicon is in the range of 0.11 to 0.18 micrometers . The OPC model begins with a Hopkin's formula for aerial image calculation and is tuned to fit the measured CD data, using a commercially available software. The OPC models are anchored at a set of selected CD dat including linearity, line-end pullback, and linewidth as a function of pitch. It is found that the threshold values inferred from measured CD dat vary approximately linearly with the slope of aerial image. The accuracy of the model is illustrated by comparing the simulated contour using the OPC model and measured SEM image. The implementation of OPC models at both active and gate is achieved using two approaches: (1) to optimize the mask bias and sizes of hammerhead and serifs via a rule based approach; and (2) to correct the SRAM cell layouts by OPC model. The OPC models developed have been successfully applied to 0.18 micrometers technology in a prototyping environment.
KEYWORDS: Optical proximity correction, Reticles, Optical lithography, Logic devices, Scanning electron microscopy, Prototyping, Lithography, Process modeling, Transistors, Digital signal processing
The evaluation of 'future' SRAM designs often involves aggressive patterning techniques. This is especially true for the prototyping stage of a product because the target 'production' tools are either unavailable or suffer from immature processes. This paper describes an OPC implementation method for 0.18 micrometers technology production of small SRAM cells of logic gate levels. A model based proximity correction has been applied to compensate the pattern distortions encountered in DUV lithography patterning. The first step is to generate a process specific empirical model for OPC simulation. To judge the accuracy of the OPC model, a set of linewidth measurements including linewidth versus pitches and linewidth versus linearity could be used to do a model prediction verification. However, linewidth confirmation is only in 1D. A 2D confirmation is important to ensure the success of OPC because there are lots of irregularly shaped layouts in a random logic device. The validity of OPC model prediction also needs to be verified for low contrast areas in patterning using focus exposure matrices by comparing the printed result to the model simulation. This procedure is very important in pushing chip density. Some experimental result from our approaches are discussed in this paper.
The effectiveness of two methods of optical proximity correction based on feature biasing and subresolution assisting features is compared by simulation and experiments. Parameters examined are overlapping focus- exposure windows for dense lines, semi-isolated and isolated lines, and line-end shortening. Binary and phase-shifting masks containing test and real IC design features are proximity corrected either by commercial software (in the case of feature biasing) or by manual correction using optimized size and placement of assisting features. The results indicate that, while both methods are effective in reducing optical proximity effects, the feature-assisted method is more advantageous in many cases.
Defect printability was investigated to assess the reticle defect size tolerance for 0.50 micrometers wafer lithography through the study of programmed reticle defect within line/space pairs. Improvement in the recent generation of steppers with higher numerical aperture and the drive toward design shrinks and 0.35 micrometers wafer technology has made the printability of smaller defects more important. We have studied the printability of opaque and thin flat transparent defects with reticle fabricated with both types of defects ranging in size from 0.3 to 3.0 micrometers . These defects are located on edge and between 2.5 micrometers line/space pairs. Using a 0.60 NA i-line stepper, wafers were printed with four illumination methods: standard with sigma of 0.60, quadrapole, annular, and higher coherence with sigma of 0.30 and the results were observed on a SEM. In addition, the reticle defects were characterized and the measured sizes simulated for further validate the observed results. Transparent defects larger than 0.5 micrometers showed greater printability than their opaque counterparts but had similar printability at the smaller sizes for all illumination methods. Opaque center defects had more influence on CD (critical dimension) loss than those on edge for standard and quadrapole illuminations but were comparable for annular and higher coherence illuminations. With a 10% loss of CD as the tolerance, defect sizes of 0.4 micrometers for opaque and 0.35 micrometers for transparent were determined to be the maximum acceptable for printability of 0.5 micrometers line/space at the wafer plane.
Phase shift has been seen by many as a route to increase the resolution capability of optical microlithography beyond the Rayleigh criterion. The initial enthusiasm with which this technology was greeted has been moderated by the realization that prior to its practical application many technical challenges must be overcome. Nevertheless progress has been made. The question to be answered is no longer whether phase shift works, but rather which phase-shift approach and manufacturing technique provide the best practical solutions. We compare three techniques to build alternating phase-shift reticles: (1) deposited spin-on glass (SOG), (2) chemical vapor deposition (CVD) silicon dioxide, and (3) etched quartz. The merits of each approach are judged in terms of lithographic performance, ease of manufacture, and reliability. We condude that the SOG approach offers the best short-term solution to the manufacture of alternating phase-shift masks, although its lithographic performance is somewhat inferior to the other two and its long-term reliability remains to be determined. For deposited oxide to be a viable long-term approach, the oxide must be deposited under the chrome; for etched quartz, the roughness and defect density must be controlled.
We have investigated the use of annular illumination on a KrF excimer laser stepper ((lambda) equals 248 nm) working near the resolution limit of the lens. The numerical aperture of the lens was 0.48 and the illuminator-lens combination produced a partial coherence of 0.44. With a central obscuration equal to 75% of the diameter of the illuminator aperture in place and using a surface-imaging resist process, we have increased the depth of focus for 0.25 micrometers dense lines and spaces from 0.9 micrometers at one point in the imaging field to 1.5 micrometers . Performance for dense contacts was also improved. These improvements demonstrate the feasibility of 0.25 micrometers technology with deep-UV lithography.
Phase shift technology shows promise to extend the useful resolution and focus latitude to contemporary optical steppers. If successful in application, this represents significant cost savings to the manufacturing wafer fobs provided that the steppers can be used or modified to take advantage of phase-shift techniques. In this paper we explore the limits of phase-shift lithography, particularly at i-line. We do this following a two-fold approach: a) using simulations and b) collecting experimental data using different resist processes and phase-shift techniques. We conclude that using state-of-the-art photoresist processes and phase-shift techniques, i-line optical lithography can be extended to the 0.25 ?m regime.
We report here the initial lithographic evaluation of AZ DN-21, a commercial, negative tone, aqueous alkali developable, chemically amplified resist. The resist was exposed with 248 nm light from a KrF laser on a Canon deep UV stepper with NA 0.37. Feature sizes down to 0.35 microns were printed with good focus and exposure latitude. The resist profiles are nearly vertical with a slight undercutting at the bottom of the feature and a slight rounding of the top. We also report some initial results from a study of the effects of delays in resist processing. For a given dose, delays in the processing increased the measured linewidths. Results from a calculation of the effective activation energy for crosslinking are also presented. For the PEB temperatures investigated, the effective energy was found to be a function of the PEB temperature.
The techniques used in the experimental characterization of thin membranes are considered for their potential use as mask blanks for x-ray lithography. Among the parameters of interest for this evaluation are the film's stress, fracture strength, uniformity of thickness, absorption in the x-ray and visible spectral regions and the modulus and grain structure of the material. The experimental techniques used for measuring these properties are described. The accuracy and applicability of the assumptions used to derive the formulas that relate the experimental measurements to the parameters of interest are considered. Experimental results for silicon carbide and diamond films are provided. Another characteristic needed for an x-ray mask carrier is radiation stability. The number of x-ray exposures expected to be performed in the lifetime of an x-ray mask on a production line is on the order of 107. The dimensional stability requirements placed on the membranes during this period are discussed. Interferometric techniques that provide sufficient sensitivity for these stability measurements are described. A comparison is made between the different techniques that have been developed in term of the information that each technique provides, the accuracy of the various techniques, and the implementation issues that are involved with each technique.
Kinematically mounted x-ray lithography masks are investigated to optimize various design parameters. Given the limited error budget for x-ray mask mounting, it is essential to minimize the mechanical distortions in the exposure area. Three-dimensional finite element models of the support ring with a membrane are used to analyze the gravitational effects for both the horizontal (e-beam patterning) and vertical mounting (synchrotron exposure). In-plane and out-of-plane distortions of the membrane are computed and the nodes in the patterned area are uniquely mapped. Results of the finite element calculations show that the mask distortions can be minimized by optimizing the design of the support ring in conjunction with the holding mechanism. The actual cross section of the ring is designed in correlation with the specifications on the position of the mount. Several design rules are developed from the analyses, relating the axis or rotation of the cross section with the radial position of the mount. Results of this study offer guidelines in choosing the optimum mask parameters considering the parametric designs presented.
Several chemically-amplified resists, positive and negative, have been evaluated for synchrotron x-ray lithography. Some have shown sensitivities as low as 10.1 mJ/cm2. Linewidths of 0.3 micron have been achieved in 1 micron thick single-layer resist with vertical sidewalls and good process latitude, at an x-ray dose of below 50 mJ/cm2. The chemically amplified resists are processed similarly to conventional resists using metal ion free aqueous base developers. Data re presented for resists from Shipley, Rohm and Haas, and Hoechst AG. Lithographic exposures were performed with the University of Wisconsin's Aladdin synchrotron, using the ES-1 beamline of the Center for X-ray Lithography.
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