The EUV mask is protected from particle contamination during exposure by the EUV pellicle, which is constructed from a membrane that is not attached to anything. The pellicle, which is made up of carbon nanotube (CNT) films, has excellent EUV transmission, low reflectivity, and mechanical durability. To evaluate the quality and dependability of the CNT pellicle for the purpose of optimizing the manufacturing process, porosity, bundle size, and particle size distribution are measured utilizing TEM or SEM images and specialized image processing techniques. This article presents a methodology that is specifically designed for processing TEM or SEM images of CNT membranes. Our methodology employs an auto-binarized technique to accurately determine the edge contour from images, and subsequently extract the distribution of each indicator through length or area calculations along the edge. The accuracy of our methodology has been verified through testing using a set of binarized standard reference images. Additionally, we evaluated the practical application of our methodology by comparing CNT membranes with different treatments to determine its sensitivity. We further demonstrated the feasibility of our method by comparing CNT membranes that have undergone varying degrees of hydrogen plasma treatment to the existing Raman D-band to G-band intensity ratio (D/G ratio).
The high numerical aperture EUV exposure systems aim to target a 16-nm pitch to extend Moore's law throughout the next decade. However, thinner photoresist layers and worsened stochastic effects due to photons hitting the wafer at a shallower angle is a major concern. Furthermore, the projection optics utilize an anisotropic reduction factor, which remains an open issue, requiring a dual "half-field" mask exposure sequence or a 12-inch mask for each high-NA EUV layer. Therefore, the use of attenuated phase-shift masks (APSM) to extend 0.33NA to a 28-nm pitch becomes relevant. We will discuss the prospects on optical properties refractive index (n,k) optimization with material selection, feasibility of achieving a 28-nm pitch, 3D effect mitigation and the impact of mask tonality (dark tone vs clear tone). Finally, the challenges on the needs of new APSM materials that meet the requirements of high temp thermal stability, durability under mask clean solution, its dry etching characteristics, the corresponding repair process will be addressed and the experimental results on the Ru-based candidates will be shown.
EUV Mask for High Volume Manufacturing of semiconductor device have already became accomplished facts. Therefore, developing a flexible and controllable process capability for various film stack EUV blank structure and production is crucial. The requirements of high compatible process window need to sustain 1-nm critical dimensions (CD) control and etch stop on capping layer with zero damage. For conventional EUV blank, dual layer TaN substrate is proposed as state-of-the-art EUV photomask blank absorber material being comprehensively evaluated. Film stack material needs to be co-optimized with developing and etching process to keep pattern profile/fidelity, capping layer quality and durability, and defect density. Hence first of all, the novel etching strategy for mitigating capping layer damage to have better Ru durability improvement will be reported. Secondly, the developing process optimization to lower the defect counts caused by wettability change due to various absorber material will show. Finally, the pattern fidelity change caused by various etching selectivity between hard mask and absorber will be discussed in this paper.
5d transition metal Pt is one of the classical spin Hall materials for efficient generation of spin-orbit torques (SOTs) in Pt/ferromagnetic layer (FM) heterostructures. However, for a long while with tremendous engineering endeavors, the damping-like SOT efficiencies (ξDL) of Pt and Pt alloys are still limited to ξDL<0.5. Here we present that with proper alloying elements, particularly 3d transition metals V and Cr, the strength of the high spin Hall conductivity of Pt (σSH∼6.45×105(ℏ/2e)Ω−1⋅m−1) can be developed. Especially for the Cr-doped case, an extremely high ξDL∼0.9 in a Pt0.69Cr0.31/Co device can be achieved with a moderate Pt0.69Cr0.31 resistivity of ρxx∼133μΩ⋅cm. A low critical SOT-driven switching current density of Jc∼3.16×106A⋅cm−2 is also demonstrated. The damping constant (α) of Pt0.69Cr0.31/FM structure is also found to be reduced to 0.052 from the pure Pt/FM case of 0.078. The overall high σSH, giant ξDL, moderate ρxx, and reduced α of such Pt-Cr/FM heterostructure makes it promising for versatile extremely low power consumption SOT memory applications.
In E-beam lithography, the double or multiple Gaussian kernels used to describe the electron scattering behavior
have been discussed extensively for critical dimensions (CDs) larger than the e-beam blur size. However in e-beam
direct write on wafer, CD dimensions are close to the beam blur size because of requirements in both resolution and
throughput. This situation gives rise to a severe iso-dense CD bias. Hence the accuracy of the modeling kernel is
required to achieve a larger common process window.
In this paper we present contour-based kernel modeling and verification for e-beam lithography. The edge contours
of CD-SEM images of the contact hole array pattern with duty ratio splits are used in this Gaussian kernel modeling
study. A 2-step optimization sequence is proposed to improve the fitting efficiency and robustness. In the first step,
roundness is the primary and the most effective index at the corner region which is sensitive to determine the beam blur
size. The next step is to minimize the deviation of the through-pitch proximity effect by adjusting the ratio of the electron
backscattering to the electron forward scattering. The more accurate cost index, edge placement error, is applied in the
subsequent optimization step with constrained beam blur sizes extracted from the previous step. The optimum modeling
kernel parameters can be obtained by the lowest cost deviation of the simulation contours and the CD-SEM extracted
edge contours after optimization iterations. For early study of the proximity impact on future EBDW systems, the
exposure experiment is performed on an EBM-8000 mask writer to build the modeling kernel. The prediction accuracy
of the optimum modeling kernel on 60-nm features with different pattern densities is also verified experimentally to be
within 1.5 nm.
The incident surface power density in Massive Electron-beam Direct Write (MEBDW) during exposure is ~105 W/cm2, much higher than ~8 W/cm2 ArF scanners and 2.4 W/cm2 EUV. In addition, the wafer’s exposure in vacuum environment makes energy dissipation even harder. This thermal effect can cause mechanical distortion of the wafer during exposure and have has a direct influence on pattern placement error and image blur. In this paper, the thermo mechanical distortions caused by wafer heating for MEB system of different electron acceleration voltages have been simulated with finite element method (FEM). The global thermal effect affected by the friction force between the wafer and the wafer chuck as well as different thermal conductivities of the chuck material are simulated. Furthermore, the thermal effects of different lithography systems such as EUV scanners and conventional optical scanners are compared. The thermal effects of MEBDW systems are shown to be acceptable.
About 13-Terabyte data for Massive e-beam direct-write lithography (MEBDW) system, a potential solution for highvolume
manufacturing (HVM) of 10-nm and beyond technology nodes in a 26 mm x 33 mm field of layout, is required.
Therefore cost reduction on data storage and transmission through development of high compression rate of lossless data
and high throughput real time decompression algorithms is necessary.
In this paper, an instruction-based hybrid method (IBHM) is proposed. It is an asymmetric scheme to hybrid simple
compression methods. The decompression is achieved by instruction-based decoding. The input layout image is
partitioned into different fragments, compressed and encoded into instructions. On the MEBDW system side, the
encoded bit-stream is decoded by the IBHM decoder. The function of this decoder is to execute only a minimal number
of simple instructions, thus the decoder can be implemented with low gate-count on ASIC. Simulation results show that a
single IBHM decoder is capable of providing an output data rate as high as ~50 Gbps in various masking layers.
Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron
beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance
of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the
DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits
appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron
image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first
realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is
presently nearing completion. The new version includes several advances intended to make it more suitable for
application in commercial lithography systems. We will discuss the innovations and compromises in the design of this
next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still
more advances will be needed. Some of the directions in which this technology can be extended will be described.
KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.
KEYWORDS: Scattering, Electron beam lithography, Data modeling, Laser scattering, Critical dimension metrology, Monte Carlo methods, Backscatter, Photomasks, Lithography, Electron beams
Electron beam lithography is a promising technology for next generation lithography. Compared to optical
lithography, it has better pattern fidelity and larger process window. However, the proximity effect caused by the
electron forward scattering and backscattering in the resist and the underlying substrate materials has a severe influence
on the pattern fidelity when the required critical dimensions (CD) are comparable to the electron beam blur size.
Therefore, an accurate electron scattering model and a proper proximity correction play a vital role in electron beam
lithography. In this paper, we describe the model accuracy of electron scattering in terms of multiple Gaussian kernels
with an in-house proximity error correction to reduce proximity error with much better accuracy and more
self-consistency than the double Gaussian kernel on the 100-keV electron energies. The impact of various Gaussian
kernels used in the proximity correction on the lineation of typical patterns is also addressed.
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half
pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL)
technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing
system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL
system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable
of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons
are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The
DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed.
Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below
the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the
REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled
DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of
over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron
beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern
scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in
both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying
the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design
improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current
chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be
presented.
Multiple e-beam direct write lithography (MEBDW), using >10,000 e-beams writing in parallel, proposed by
MAPPER, KLA-Tencor, and IMS is a potential solution for 20-nm half-pitch and beyond. The raster scan in MEBDW
makes bitmap its data format. Data handling becomes indispensable since bitmap needs a huge data volume due to the
fine pixel size to keep the CD accuracy after e-beam proximity correction (EPC). In fact, in 10,000-beam MEBDW, for a
10 WPH tool of 1-nm pixel size and 1-bit gray level, the aggregated data transmission rate would be up to 1963 Tera bits
per second (bps), requiring 19,630 fibers transmitting 10 Gbps in each fiber. The data rate per beam would be <20 Gbps.
Hence data reduction using bigger pixel size, fewer grey levels to achieve sub-nm EPC accuracy, and data truncation
have been extensively studied.
In this paper, process window assessment through Exposure-Defocus (E-D) Forest to quantitatively characterize the
data truncation before and after EPC is reported. REBL electron optics, electron scattering in resist, and resist acid
diffusion are considered, to construct the E-D Forest and to analyze the imaging performance of the most representative layers and patterns, such as critical line/space and hole layers with minimum pitch, cutting layers, and implant layers, for the 10-nm, and 7-nm nodes.
KEYWORDS: Electron beam lithography, Semiconducting wafers, Electroluminescence, Lithography, Monte Carlo methods, Reflectivity, Electron beams, Direct write lithography, Silicon, Computer aided design
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 16 nm technology node
and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) targeting high-volume 16 nm
half pitch (HP) production. This paper reviews progress in the development of the REBL system towards its goal of 100
wph throughput for High Volume Manufacturing (HVM) at the 2X and 1X nm nodes. We will demonstrate the ability to
print TSMC test patterns with the integrated system in photoresist on silicon wafers at 45 nm resolution. Additionally,
we present simulation and experimental results that demonstrate that the system meets performance targets for a typical
foundry product mix.
Previously, KLA-Tencor reported on the development of a REBL tool for maskless lithography at and below the 16 nm
HP technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards
developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam
direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been
used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 16 nm HP technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVM.
Unlike optical systems, electron-charging effect is a concern for e-beam lithography. Accumulated charge on the
resist will perturb the route of incident electrons, resulting in pattern distortion or failure. Therefore, reducing charge
accumulation becomes an important topic for high-pattern-density e-beam applications.
In this paper, we used a conductive material as the resist substrate for charging effect evaluation. The e-beam source
from CD-SEM (Critical Dimension SEM) was initially used to conductive performance qualification. When comparing
with non-conductive BARC, we found that the experimental conductive material has an additional 11% to 14%
resist-shrinkage than a non-conducting BARC. However, we cannot repeat this phenomenon in the multiple-e-beam
(MEB) imaging tool. From Monte Carlo simulation, the electrons deeply penetrate through the substrate instead of being
trapped in the resist substrate. It further indicates that although conductive bottom layer can dissipate electron effectively
for surface charging, the film scheme as well as tool grounding are also important for minimizing the charging effect.
KEYWORDS: Field programmable gate arrays, Data storage, Maskless lithography, Photomasks, Electron beams, Semiconducting wafers, Data processing, Prototyping, Data conversion, Logic
Electron beam lithography has been used in the production of integrated circuits for decades. However, due to the
limitation of throughput it was not a viable solution for high volume manufacturing and its biggest application is the
production of semiconductor masks. For many considerations it has particularly now become desirable to eliminate the
semiconductor mask and introduce maskless lithography for semiconductor fabrication. Multiple Electron Beam
Maskless Lithography (MEBML2) has been proposed as a solution to overcome the traditional source current limitation
of an electron beam system by using many thousands of parallel electron beamlets to write a pattern directly on the
wafer.
In developing the MEBML2 tool the challenges have shifted and, in absence of the mask, the system data path has
emerged as one of the central challenges. The main theme in the data path development is bandwidth. The required raw
bandwidth at the patterning beams is determined by throughput and resolution, i.e. pixel size and number of intensity
modulation levels. To achieve a production worthy throughput at 10 wafers per hour in a Gaussian-beam-based maskless
lithography system, by writing 3.5-nm pixels at 2 levels (on/off) which is required for the 22-nm lithography node, the
required aggregate bandwidth at the beam blanker array is up to 45 Tbit/s. Such a large bandwidth requirement means
that the data path architecture is mainly characterized by the bandwidth of the data streams in the system. Compression
techniques can be used to reduce the intermediate data stream bandwidth requirements and consequently lead to
simplifying the system design, reducing power consumption and footprint, but come at the cost of increased data
processing complexity and possible limitations on throughput.
In this paper we will show results from the development of a prototype data path for the Gaussian-beam-based maskless
lithography system. A new concept for data processing and storage is proposed. The vertex-based processing and storage
technique is adopted to reduce memory usage considerably, with only modest requirements on the hardware resources. It
reveals that a realistically implementable data path system for the maskless lithography tool in high volume
manufacturing is feasible.
KEYWORDS: Raster graphics, Critical dimension metrology, Semiconducting wafers, Data transmission, Electron beam lithography, Tolerancing, Optical fibers, Maskless lithography, Electron beam direct write lithography, Mask making
Massively E-beam maskless lithography (MEBML2) is one of the potential solutions for 32-nm half-pitch and
beyond. In the past, its relatively low throughput restricted EBDW development to mostly mask making, small volume
wafer production and prototyping. Recently the production worthy ML2 approaches, >10,000 e-beams writing in
parallel, have been proposed by MAPPER, KLA and IMS. These approaches use raster scan in pattern writing. Hence
the bitmap is certainly the final data format.
The bitmap format used to have huge data volume with fine pixel size to maintain the CD accuracy after electron
proximity correction (EPC). Data handling becomes necessary, especially on data transmission rate. The aggregated data
transmission rate would be up to 1963 Tera bits per second (bps) for a 10 WPH tool using 1-nm pixel size and 1-bit gray
level. It needs 19,630 fibers each transmitting 10 Gbps. The data rate per beam would be >20 Gbps in 10,000-beam
MEBML2. Hence data reduction using bigger pixel size to achieve sub-nm EPC accuracy is crucial for reducing the fiber
number to the beam number.
In this paper, the writing-error-enhanced-factor to quantitatively characterize the impact of CD accuracy by various
total blur in resist is reported; and we propose the vernier pattern to verify sub-nm CD accuracy and the in-house
dithering raster method to achieve sub-0.2-nm CD accuracy using multiple-nm pixel sizes, which could reduce the need
of the aggregated data rate to 11%, 33%, 44% and 79% of 1963 Tbps on 22-nm, 16-nm, 11-nm, 8-nm node respectively.
E-beam direct write (EBDW) is one of the potential solutions for technology nodes of 28-nm half-pitch (HP) and
beyond. Throughput limitation confined its development mostly to small-volume prototyping. Recently, proposals have been
made to achieve throughput greater than 10 wafers per hour (WPH) on a single column with >10,000 beams writing in
parallel (MEBDW), or even greater than 100 WPH by further clustering multiple columns within a typical production-tool
footprint. The MAPPER concept contains a CMOS-MEMS blanker array driven by high-speed optical data path architecture to simultaneously control >10,000 beams, switching them on and off independently.
The MAPPER Pre-Alpha Tool with a 110-beam, 5-keV column and a 300-mm wafer stage has been installed in a semiconductor manufacturing cleanroom environment and is ready for imaging test. In this paper, the resist imaging results
of 110-beam parallel raster-scan writing for 30-nm half-pitch (HP) dense hole on 300-mm wafer is shown. The challenges of
implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including resolution, local variation, focusing, energy latitude, proximity effect correction and electron scattering model fitting of hole patterning are discussed. Similar to mask-error-enhanced-factor (MEEF), the new writing-error-enhanced-factor (WEEF) to describe the impact of writing error, is introduced.
E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern
to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the
law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible
solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour
(WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further
clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS
blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of
beams, switching them on and off independently.
The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for
imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit
layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2)
in mass production environment, including illumination, focusing, and CD uniformity, are discussed.
The Multiple E-beam Direct Write (MEBDW) technology has been considered a promising solution for the next
generation lithography to delineate 32-nm half-pitch and beyond. A low-energy, say 5 keV, e-beam direct writing system
has advantages in lower exposure dosage, less heating effect on resist, and less damage to devices underneath, comparing
with a high energy one, such as 50 keV or 100 keV. However, the low-energy electron-beam is easily blurred due to
forward scattering in the substrate due to its shallow penetration and hence loses resolution. In this paper, variables
affecting patterning fidelity of a raster-scan MEBDW system are investigated.
In order to realize a MEBDW system with acceptable throughput, a relatively large beam size is chosen for sufficient
beam current to sustain throughput while maintaining enough resolution. The imaging resolution loss and the proximity
effect, due to beam blurring through the resist, have been observed. The in-house software MOSES, incorporating the
Monte Carlo simulation and the Double Gaussian model was used to evaluate 1-D and 2-D pattern fidelity with various
exposure conditions. The line width roughness, which represents 1-D fidelity, was evaluated on 32-nm dense lines.
Pattern fidelity of 2-D features such as the zigzag poly line and dense metal patterns was also examined. The impact to
LWR of using the edge dithering method, instead of dosage modulation, to control the line width accuracy beyond the
pixel size was studied.
We investigate the performance of nominally 6% attenuated phase shifting masks (AttPSM) for 193nm in printing 0. 13?m contact holes using a variety of shifter materials. Imaging performance of AttPSMs with various shifter materials, transmission, and side wall angles is presented and compared. Aerial images from binary and phase-shifting masks are analyzed by a 193nm aerial image acquisition tool to distinguish the contribution of the mask from that of the resist process. Compared to binary masks, AttPSMs are capable of printing 0.13?m contact holes with twice the DOR Our results indicate that 193nm AttPSM holds promise for patterning contact hole in the manufacturing of next generation logic devices.
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