This paper investigates the electrostatics and carrier transport in nanowires with double heterostructures (DH). The
particular interests include strong fringing field and weak screening effects resulting from the increased surface to
volume ratio in nanowires. A general device simulator, PROPHET, is employed for a model nanowire structure with
Al0.2Ga0.8N/GaN DH. Our simulations show that in general, the junction depletion width in the active region increases
for nanowire based DH devices. The impacts of such effect on carrier injection in nanowire devices as well as the roles
of forward biasing and material compositions are also investigated.
The unique properties of semiconductor nanowires pose promising applications in optoelectronics such as photo-detectors
and lasers. Owing to the increased surface/volume ratio, nanowire-based p-n junctions exhibit qualitatively
different properties from those of bulk cases. These include weaker electrostatic screening and stronger fringe field
effects. This work employs a general device simulator, PROPHET, to numerically investigate the unique electrical
properties of p-n junctions in single nanowires and nanowire arrays. The implications of such effects in nanowire-based
photo-detector design are also examined.
The domino circuit failure is due to competing requirements of the keeper and the NMOS logic transistors that cannot be satisfied simultaneously in order to achieve the noise margin and performance objectives. Domino keeper transistor has to be upsized to compensate for the subthreshold leakage and gate leakage currents that discharge the dynamic node in deep sub-100nm technologies. Domino multiplexer can fail when the fan-in number is greater than 14 for the noise margin of 0.1 Vdd, where the noise margin is defined as the input voltage that causes 10% voltage drop at the dynamic node of Domino. In simulation, 45nm BSIM4 models were used with the power supply voltage of 0.8V. To solve this problem, we propose a dual gate oxide thickness (Tox) implementation for high fan-in Domino. With proper dual gate oxide thickness assignment, subthreshold leakage and gate leakage that discharge the dynamic node are suppressed with the keeper size reduced. Proposed circuit not only prevents the possible failure in high fan-in Domino, but also reduces the delay and power consumption due to decreased contention between the keeper and NMOS logic tree. For 14-bit domino multiplexer, proposed circuit is 56% faster with 66% less power consumption and without area penalty, compared to single Tox domino.
The leakage power consumption in deep sub-100nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current, the gate leakage problem poses a significant design challenge. We introduce gate leakage tolerant circuits. We describe two new circuit techniques to suppress gate leakage currents in dual Vt Domino circuits. In standby mode, proposed circuits generate low inputs and low outputs for all Domino stages to suppress gate leakage currents in the NMOS logic tree. Simulation results using 45nm BSIM4 SPICE models for 32-bit adders show that adders using the two proposed circuits can reduce the standby gate leakage by 66% and 90%, respectively. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.
As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor's performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit's performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.
Conference Committee Involvement (6)
Microtechnologies for the New Millennium
2 May 2007 | Maspalomas, Gran Canaria, Spain
Smart Structures, Devices, and Systems III
11 December 2006 | Adelaide, Australia
VLSI Circuits and Systems II
9 May 2005 | Sevilla, Spain
Smart Structures, Devices, and Systems II
13 December 2004 | Sydney, Australia
Microelectronics: Design, Technology, and Packaging
10 December 2003 | Perth, Australia
VLSI Circuits and Systems
19 May 2003 | Maspalomas, Gran Canaria, Canary Islands, Spain
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