While technology is being developed, design rules undergo a number of revisions. An initial lithography model built with test patterns before the revisions inherently become inaccurate for the revised patterns. Preparing a new test layout and updating a lithography model every time design rules are revised is not practical, and cannot be a solution. We prepare some synthetic patterns in addition to initial test patterns. Synthetic patterns originate from popular test pattern generator (TPG), while projected design rule changes are taken into account. A challenge is to sort out the synthetic patterns which are really necessary in building a generic lithography model when they are used together with test patterns. Each pattern, either synthetic or test, is identified in image parameter set (IPS) space. For each test pattern in IPS space, two concentric spheres are drawn; outer one indicating the region where revised versions of test pattern may exist, and inner one indicating the region which is well covered by test pattern alone. Synthetic patterns that reside in the region bounded by the two spheres are kept, while the others are dropped. Clustering is now performed on test patterns and synthetic patterns separately, and representative pattern is drawn from each cluster. When a set of representative patterns are used to build a lithography model in 10nm memory devices, it achieves 43.5% lower CD root mean square error (RMSE) for revised design layout compared with only using a set of initial test patterns.
Calibration pattern coverage is critical for achieving a high quality, computational lithographic model. An optimized calibration pattern set carries sufficient physics for tuning model parameters and controlling pattern redundancy as well as saving metrology costs. In addition, as advanced technology nodes require tighter full chip specifications and full contour prediction accuracy, pattern selection needs accommodate these and consider contour fidelity EP (Edge Placement) gauges beyond conventional test pattern sets and cutline gauge scopes. Here we demonstrate an innovative pattern selection workflow to support this industry trend. 1) It is capable of processing a massive candidate pattern set at the full chip level. 2) It considers physical signals from all of the candidate pattern contours. 3) It implements our unsupervised machine learning technology to process the massive amount of physical signals. 4) It offers our users flexibility for customization and tuning for different selection and layer needs. This new pattern selection solution, connected with ASML Brion’s MXP (Metrology of eXtreme Performance) contour fidelity gauges and superior, accurate Newron (deep learning) resist model, fulfills the advanced technology node demands for OPC modeling, thus offering full chip prediction power.
Sub-resolution assist features (SRAFs) are inserted in mask layout to improve the manufacturing process window of main patterns. SRAFs should be large enough to maximize their effect, but they are not intended to be printed on photoresist (PR). An accurate method of SRAF printing prediction is important to assure that no SRAFs are actually printed. We apply a machine learning model, specifically artificial neural network (ANN), for fast and accurate SRAF printing check (named ML- SPC). Polar Fourier transform signals and local layout densities are extracted from each SRAF pixel and its surroundings, and are provided to ANN. The area sum of member pixels that are predicted to be printed is used to determine the final printability of SRAF. Training data is carefully sampled so that similar number of printed and non-printed data are used for training; cost function is adjusted in such a way that missing predictions are treated more importantly than false alarms. When ML-SPC is applied to 10nm memory devices, it achieves 11% of false alarms while popular MTA method reports 24%. In addition, ML-SPC is faster than MTA by about 2.7 times.
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