We are developing a new macroinspection technology for through silicon via (TSV) process wafers. We present new simulation results obtained with a fine TSV model and new optics. The optical system includes not only diffraction optics, but also polarization optics, by which we can detect changes in the profile (cross-sectional shape) of repeated patterns by detecting changes in the polarization status of reflected light. We confirmed the performance of the methodology by optical simulation using a model of via patterns with 1 μm diameter and 10 μm depth as a typical intermediate-interconnect-level TSV.
A new methodology for inspection of through silicon via (TSV) process wafers is developed by utilizing an optical diffraction signal from the wafers. The optical system uses telecentric illumination and has a two-dimensional sensor for capturing the diffracted light from TSV arrays. The diffraction signal modulates the intensity of the wafer image. The optical configuration is optimized for TSV array inspection. The diffraction signal is sensitive to via-shape variations, and an area of deviation from a nominal via is analyzed using the signal. Using test wafers with deep via patterns on silicon wafers, the performance is evaluated and the sensitivities for various pattern profile changes are confirmed. This new methodology is available for high-volume manufacturing of future TSV three-dimensional complementary metal oxide semiconductor devices.
A new methodology for inspection of TSV (Through Silicon Via) process wafers is developed by utilizing an optical
diffraction signal from the wafers. The optical system uses telecentric illumination and has a two-dimensional sensor in
order to capture the diffraction light from TSV arrays. The diffraction signal modulates the intensity of the wafer image.
Furthermore, the optical configuration itself is optimized. The diffraction signal is sensitive to via-shape variations, and
an abnormal via area is analyzed using the signal. Using the test wafers with deep hole patterns on silicon wafers, the
performance is evaluated and the sensitivities for various pattern profile changes were confirmed. This new methodology
is available for high-volume manufacturing of the future TSV-3D CMOS devices.
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