The paradigm switch to a reflective mask design for EUV lithography has proven to be challenging. Within the Horizon2020 PIn3S program Zeiss and imec are collaborating to address some of these challenges. In this work, an EUV mask with a collection of programmed defects representative for the 3nm technology node was reviewed. Defect printability at wafer level was analyzed after exposure on the ASML NXE:3400B by SEM. Furthermore, the mask was analyzed on the Zeiss AIMS® EUV platform and by SEM. For P36 (1x) 1:1 L/S programmed extrusions we have demonstrated that AIMS® EUV can be used to predict ADI local defect widths as well as (μ)bridge printability. Moreover, from P36 to P32 the mask spec regarding allowed opaque L/S extrusion widths needs to be tighter considering an earlier onset of ADI (μ)bridge printability and a stronger than expected ADI defect width increase through pitch.
For future technology nodes, highly accurate dimensional metrology will become more and more important. At this stage,
measuring layer thickness in planar test structures or geometrical dimensions in simplified proxy structures may be not
sufficient for accurate control of highly sophisticated process steps. Model-based dimensional metrology has the
potential to provide critical parameters of interest for process control in high volume manufacturing, while during
process and technology development the constrained flexibility of models and the required model-building efforts may
be a serious limitation. On the other hand, model-free dimensional metrology may provide sufficient flexibility for
process development, while in some cases it may not be production-worthy in high volume manufacturing. This article
details advantages and disadvantages of the different methods during the lifetime of a product starting from early
development to high-volume production.
KEYWORDS: Line edge roughness, Line width roughness, Electron beam direct write lithography, Amplifiers, Metrology, Cadmium, Electron beams, Lithography, Critical dimension metrology, Modulation
Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current
lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation
of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to
test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear
understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor
gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained
results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR.
Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the
effect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is more
important than that of LER for future lithography developments.
The precise reporting of critical dimension (CD) features on photolithographic masks is an essential part of
the mask production process. A wide range of external (standardization by national institutes) and internal
(standardization within mask houses to match different tools) methods has been set up to ensure calibration
consistency for the simple one dimensional case. One of the current developments is to expand these
concepts to area measurements. This is to achieve better reproducibility of CD tools and to achieve a better
characterization of contacts with respect to their imaging behaviour in wafer scanners. Here, we report some
very fundamental constrains of this approach that have to be taken into account regardless of the actual
measurement strategy. The major result is that for two dimensional contacts the shape has to be considered.
This is due to the fact that the usually constant offset for calibration of critical dimensions in one dimension
is no longer a constant but depends on the absolute size of the contact and the value of the corner rounding.
For standard values of 200 nm contacts with corner rounding of 75 nm and calibration offsets around 20 nm
maximum systematic differences of about 2nm will be obtained. Given the fact that even 40 nm calibration
differences for photomask standards can be observed even for national institutes, these systematic errors can
be easily as large as 6 nm for 200 nm structures. This systematic error clearly exceeds the road map targets
for critical dimension off-target specifications for the coming technology node. This statement is even
emphasized by the fact that in future contact layer specifications will be smaller than for lines/space layers.
Once tool independent characterization of contact areas has to be achieved, area measurement in each mask
house needs a second thought to implement these systematic constrains. Here, we show that the additional
measurement of the corner rounding ís a relatively easy method to accomplish this.
Critical Dimension uniformity (CDU) is one of the most critical parameters for the characterization of
photomasks. For years the understanding was that CDU describes a rather random fluctuation of the CD
across the mask. With more advanced CD tools and mask processes the local short-range CD variation (on a
length scale of micrometre) can be distinguished from the global CD signature (typically on a length scale of
centimetre). Recent developments in the pattern generator sector allow correcting for such global CD
signatures. This triggers the current challenge to find stable methods to characterize the global signature of
photomasks.
In our work we present matching results of a technique that calculates the CD signature using exponentially
weighted surrounding points. We investigated different CD SEM tools of different technology generations.
We show that our method allows determination of the CD signature independently of the measurement tool
with low uncertainty and moderate measurement effort. This holds even true when the CDU value is mainly
dominated by the measurement error. Thus our method provides a tool to extend the utilization of older
generation metrology tools as well as the possibility to improve the measurement capability for CD signature
of current tools.
This paper describes a method to automatically distinguish between line and space for 1:1 line space patterns in mask
metrology. As the number of measurements typically performed on a reticle is significantly higher than on a wafer,
automated CAD based CD-SEM recipe creation is essential. Such recipes typically use synthetic pattern recognition
targets instead of SEM based pattern recognition targets. Therefore, a possible different contrast between lines and
spaces on a mask cannot be utilized for distinguishing lines from spaces. We demonstrate an algorithm solution based
on the analysis of the SEM waveform profiles to identify potential L/S mix-ups and correct them automatically. The
solution allows fully automated CAD based offline recipe creation with a high success rate of distinction between lines
and spaces for 1:1 pitch cases without the necessity of editing recipes on the tool in advance of performing the
measurements.
With decreasing Critical Dimensions (CD), the negative influence of line edge roughness (LER) and line-width
roughness (LWR) on CD uniformity and mean-to-target CD becomes more pronounced, since there is no corresponding
reduction of roughness with dimension reduction. This applies to wafer metrology as well as to mask metrology. In
order to better understand the types of roughness as well as the impact of the CD-SEM roughness measurement
capabilities on the control of the mask process, the sensitivity and accuracy of the roughness analysis were qualified by
comparing the measured mask roughness to the design for a dedicated LER test mask. This comparison is done for
different LER amplitude and periodicity values and for reference structures without nominal LER using the built-in CD-SEM
algorithms for LER characterization.
In our work we discuss two approaches of offline CD-SEM recipe creation for both OPC qualification wafers and the introduction of new products to the manufacturing line using the Applied Materials OPC Check and Offline Recipe Editor (ORE) applications. We evaluate the stability of the offline created recipes against process variations for different OPC test layouts as well as for production measurements on multiple lots per week and compare the results to the performance of recipes created directly on the tool. Further, the success rate of recipe creation is evaluated. All offline recipes have been generated in advance of wafer availability using GDS data. The offline created recipes have shown pattern recognition success rates of up to 98% and measurement success rates of up to 99% for line/space as well as for contact-hole (CH) measurements without manual assists during measurement. These success rates are in the same order of magnitude as the rates typically reached by an experienced CD-SEM engineer creating the recipes directly on the tool.
KEYWORDS: Semiconducting wafers, Scatterometry, Metrology, Lithography, 3D modeling, Scatter measurement, Critical dimension metrology, Process control, Process modeling, Data processing
With critical dimensions in microelectronics devices shrinking to 70nm and below, CD metrology is becoming more and more critical, and additional measurement information will be needed, especially for sidewall profiles and profile height. Integrated scatterometry is, on the one hand, giving the needed measurement precision, and on the other hand, it enables more measurements than stand-alone metrology. Both high precision and large sampling are needed for future technology nodes. This paper shows results from several full volume DRAM applications of state-of-the-art technology nodes on 300 mm wafers. These applications include critical line/space (L/S) layers as 2D applications and contact-hole (CH) layers consisting of elliptical CH-like structures as critical 3D applications. The selected applications are significantly more challenging with respect to scatterometry model generation than the applications presented in previous papers [1, 2]. Simultaneously, they belong to the most critical lithography steps in DRAM manufacturing. In the experiments, the influences of both pre-processes and the litho cluster on Critical Dimension Uniformity (CDU) have been investigated. Possible impacts on Run-to-Run systems like Feed-back and Feed-forward loops will also be discussed. We show that using integrated scatterometry can significantly increase the productivity of lithography clusters.
In our work we investigate the influence of averaging varying numbers of measurement structures on process stability and CD uniformity. Measurements are performed on an Applied Materials VeritySEM CD-SEM system which provides the possibility to measure several lines or contact hole structures and to yield the average and 3 sigma value of all measured structures. We show that averaging significantly improves the single tool precision up to 30%. Additionally, a long term pilot test has shown that the range of the CD distribution of selected production layers is significantly decreased reducing the contribution of the measurement to the total CD budget resulting in a yield enhancement. Further, we discuss the influence of averaging on the contribution of short-range random CD variations for CD uniformity measurements. This is done by investigating the distribution of the CD difference between adjacent structures across the wafer. We show that increased averaging significantly reduces the contribution of random CD variations to the CD budget.
In our work, Tokyo Electron's iODP103 (integrated Optical Digital Profilometry) technology is used for integrated measurements on a next-generation Lithius Clean Track on after develop inspect (ADI) 300mm wafers. We show that single tool precision and tool-to-tool matching of three integrated systems fulfill the precision requirements of the 70nm DRAM technology node. Further results from a long-term pilot test using integrated scatterometry in a full-volume DRAM production of the 110nm technology node on 300mm wafers are also discussed. The data from our experiment is collected and charted in fab monitored statistical process control (SPC) charts, and compared to the charts from the POR CD-SEM measurements. The sampling plans are optimized in such a way as to perform fully integrated measurements on all wafers per lot, without throughput loss of the litho cluster. We demonstrate that the possibility of measuring all wafers per lot directly after development, in combination with the sensitivity of the method, allows the identification of effects that could not previously be identified by CD-SEM measurements alone.
KEYWORDS: Electron microscopy, Atomic force microscopy, 3D metrology, Line edge roughness, Reconstruction algorithms, Scanners, Finite element methods, Photoresist processing, Critical dimension metrology, Process control
In this work, the profile reconstruction capability of the Applied Materials NanoSEM 3-D critical dimension-scanning electron microscopy is evaluated. The system allows the fully automatic reconstruction of profiles by evaluating profiles measured at two different beam tilt angles. From two different tilt angles up to 15 deg, the reconstruction of sidewall profiles is possible in a quick and nondestructive way, even for negatively sloped profiles. The sensitivity of profile reconstruction, especially with respect to height and undercut detection in dependence of structure height and beam tilt angle, is discussed. We investigate precision and accuracy of profile reconstruction by comparing results from profile reconstruction to AFM and cross-sectional (X-SEM) results. We show that the sidewall angle can accurately be detected for 193-nm resist structures even for negatively sloped profiles. This enables the system for production use especially for monitoring of such profiles. As the profile reconstruction is done with nearly the same speed as regular top-down measurements, a clear advantage over existing monitoring techniques is obvious.
We use the LER measurement capabilities of the Applied Materials NanoSEM 3D CD-SEM for the determination of LER for different manufacturing steps of the DRAM gate layer for the 90 nm technology node and below (after develop, after hard mask-open and final inspection steps). The system allows the fully automatic measurement of the LER as a 3 sigma value for top as well as bottom LER and yields also information about the spatial frequency along the line edge. We demonstrate precision of LER measurements (3 sigma) of less than 10% of the LER for resist structures as well as for etched structures with random or artificial LER within a range from 4 to 20 nm LER. The results agree with the requirements of the ITRS roadmap for structures down to 70 nm. We show on etched poly wafers containing artificial LER that the identification of discrete frequencies is possible down to LER values of below 5 nm (3 sigma). Based on these result we investigate LER on product wafers and show that the LER of left and right line edge, repsectively, are independent of each other. Additionally, no significant discrete frequencies are detected for all process steps under investigation, although the LER amplitude varies significantly in dependence of process conditions.
In the production of sub 140nm electronic devices, CD metrology is becoming more critical due to the increased demands placed on process control. CD metrology using CD-SEM is approaching its limits especially with respect to precision, resolution and depth of field. Potentially, scatterometry can measure structures down to 50nm with the appropriate precision. Additionally, as scatterometry is a model based technique it allows a full reconstruction of the line profile and the film stack. In this work we use SE based scatterometry in the control of a 110nm DRAM WSix Gate process at the Litho and the Mask Open step. We demonstrate the use of a single trapezoid as a basic shape model in FEM and field mapping applications as well as in a high volume production test. The scatterometry results are compared to CD-SEM data. We show that for the GC Litho application, n&k variations in some of the stack materials do not affect the scatterometry CD measurement significantly.
KEYWORDS: 3D metrology, Atomic force microscopy, Scanning electron microscopy, Silicon, Deep ultraviolet, Line edge roughness, Process control, Scanners, Finite element methods, 3D image processing
In this work the profile reconstruction capability of the Appplied Materials NanoSEM 3D CD-SEM is evaluated. The system allows the fully automatic reconstruction of profiles by evaluating profiles measured at two different beam tilt angles. From two different tilt angles up to 15 degrees the reconstruction of side-wall profiels is possible in a quick and non-destructive way even for negatively sloped profiles. The sensitivity of profile reconstruction especially with respect to height and undercut detection in dependence of structure height and beam tilt angle is discussed. We investigate precision and accuracy of profile reconstruction by comparing results from profile reconstruction to AFM and X-SEM results. We show that the side-wall angle can accurately be detected for 193nm resist structures even for negatively sloped profiles. This enables the system for the production use especially for monitoring of such profiles which cannot be detected by top-down CD-SEM so far.
We use CD-SEM side-wall imaging using the Applied Materials VeraSEM 3d system as a destruction free and quick method to determine side-wall profiles. The system allows the reconstruction of profiles by tilting the SEM beam up to 6 degrees. Using two different tilt angles the reconstruction of side-wall profiles is possible in a quick and destruction free way even for negatively sloped profiles. The use of the profile analysis utility is believed to reduce cycle time significantly especially for process development and troubleshooting in production. We compare profiles obtained from the profile analysis utility of the VeraSEM 3D to X-SEM measurements to qualify this method for use in development and high volume production. For selected examples containing resist lines we investigate process windows determined from topdown CD measurements, X-SEM measurements and the profile analysis utility and compare the best stepper focus and exposure dose values obtained from these methods. It is shown how the results from the profile analysis utility can be used for process monitoring by comparing the obtained data to reference data from FEM wafers.
Reticle imaging and metrology are becoming increasingly difficult as reticle features decrease in size. This paper describes some early results of top down CD-SEM reticle imaging and metrology carried out in association with the DUV and 193 nm lithography programs at IMEC. Images of reticle features and some corresponding printed wafer patterns are presented and CD-SEM and optical measurement techniques are compared.
In the constant drive to go to smaller feature sizes, the control of the linewidth become more important than ever before, with the intra-field CD-control as a major contributor. It is expected that 248 nm lithography will be used for volume manufacturing of the 0.15 micrometers generation and may even be pushed to 0.13 micrometers . In order to do so, strong resolution enhancement technique such as aggressive optical proximity correction (OPC) and alternating phase- shifting masks (altPSM) will be needed. However a strong interaction with reticle CDs and lens aberrations is expected. With the use of state-of-the-art reticles and lenses, not only the process latitudes at one point in the field but the CD-control across the full field become very important. In this paper an illumination optimization has been done in terms of individual process latitudes, CD- proximity effect and especially the across-field CD- variation. With these optimized stepper settings, a comparison of the intra-field CD-control of binary masks with OPC and altPSM for 0.15 micrometers and 0.13 micrometers features with various duty cycles using a high NA 248nm stepper has been carried out. With binary masks the across-field CD- control for the 0.15micrometers isolated lines is not below 15nm in best focus. The use of sub-resolution assist features improved the across-field CD-uniformity as compared to the binary mask even in best focus. Over a limited focus range 150nm lines had a 3 sigma value below 15nm. It is expected that a higher NA will show this over an even larger focus range, making the assist feature sufficient for 0.15micrometers patterning with an adequate CD-control. For the 0.13micrometers lines alternating phase-shifting masks result in an across- field CD-variation below 13nm over a focus range of 0.4micrometers . For this work ,state-of-the-art reticles have been sued and no attempt was made to remove reticle CD errors from the CD-control data.
In this work, die-to-die CD-variations across a wafer are investigated as a potential important contribution to the global gate CD-control. Measuring the non-uniformity in different experiments using CD-SEM and ELM revealed different parameters, impacting the measured non-uniformity value. It will be pointed out that the measurement itself can have a significant contribution to the measured 3(sigma) -value, especially using CD-SEM, if the level in non-uniformity is low. Further on, it will be shown that the choice of resist and developer chemistry can have a high impact on the i-W CD non-uniformity. Moreover, the potential impact of exposure and track processing will be outlined, and an optimization methodology will be presented. Finally, it will be shown that gate process integration, in particular BARC- and POLY-etching, is increasing the i-W CD non-uniformity. This is affecting the ELM-results, despite the high precision and repeatability of these measurements. This ELM-variation, as well as the overall i-W CD non- uniformity should be taken into account when using ELM or CD-SEM as a metrology tool for process window characterization.
Lithography simulation tools eliminate costly and time consuming experiments allowing new processes to be developed quickly. There are excellent simulation programs that allow sophisticated modeling of the optics in current and future lithography tools. In many instances, the weak point in lithography simulations is the relatively poor capability to model resists. Sophisticated and accurate models have been developed for many technologically important i-line resists. However the models for 248nm chemically amplified resist are not as mature, and there are many resist of interest for which there are no reliable models. Even when they do exist, these full resist models are computationally expensive and not suitable for some applications such as model based optical proximity corrections. When useful models do not exist, lithographers use the aerial imaging portions of the lithography simulation tools and apply the simplest of resist models, the so-called constant threshold model. While this allows the critical dimensions to be approximated for high contrast resist, it fails to capture important aspects of most resist processes. Empirically trained resists models have come to be used where more accurate lithography simulations are required, but full resist models either do not exist or are to slow to be useful. This paper explores the use of a class of empirically trained models known as variable threshold resist models. This type of model stats with an aerial image calculation and uses a function to locally vary the threshold used to predict CDs. This type of model may be quickly trained for a specific resist process and potentially applied for a wide range of numerical aperture and partial coherence settings. We show how multiple dose and focus data can be used to train a model that includes input parameters extracted from the aerial image as well as pattern factors and exposure dose. The data present suggests that models trained with one set of optical conditions are useful at other optical settings. We also explore different approaches to validate the models and demonstrate some consider the effect of across wafer variation on the training data.
In this work, we investigate the role of low voltage reticle CD-SEM measurements on DUV lithography. We compare reticle measurements carried out on tow different CD-SEMs and optical measurements as typically carried out at mask shops. CD-SEM measurements using the 50 percent derivative algorithm on the KLA 8100ER CD-SEM and the 50 percent threshold algorithm on the Hitachi 6100 CD-SEM show good correlation with the optical measurements. As examples for the importance of LV CD-SEM reticle measurements we show the influence of proximity effects during reticle printing on CD variations on reticle level by comparing the values obtained on the reticle and on the wafer. Finally, we determine mask error factors. The MEF has to be taken into account to compare wafer and reticle CDs. We show that it does not change for wafer measurement after lithography and after poly-etch. The use of different metrology tools or electrical linewidth measurements does not influence the MEF.
This paper discuses the need for additional mask quality factors for implementation into a further roadmap. These factors are expected to affect the printed image on wafer. Especially the global idea of pattern fidelity is introduced. Low voltage scanning electron microscopy can offer the capability to mask makers to deliver this extra information. This knowledge should lead to a better understanding how mask imperfections may contribute to the overall lithography error budget. This understanding will need to rely on stronger collaboration between mask maker and mask user. Using simulation data and the so-called mask error factor, it is shown that certain mask strategies may allow larger mask error budgets.
In this paper, the intra-field critical dimension (CD) control of a KrF step&scan and step&repeat system are investigated and compared. The scanners are expected to replace the conventional steppers in the manufacturing of integrated circuit generation of 0.18 micrometer and beyond, because of the larger field size and the intrinsic improvement in intra- field CD and overlay control using comparable lens design, complexity and cost. The work has been focused on sub-0.25 micrometer critical dimensions. A reticle design for both top- down CD measurements and electrical linewidth probing has allowed massive data collection and investigation of the impact of the metrology technique in CD control studies. From this study, it can be concluded that the stepper and scanner exhibit similar CD control at best focus, but the scanner improves the CD control of the stepper if the considered focus range increases. The CD control is governed by the reticle CD non-uniformity. Focus budget calculations indicate that reticle CD ranges of 40 nm (4x) are needed to bring the CD control of 0.2 micrometer grouped lines within acceptable ranges for realistic gate levels. For isolated lines, dedicated deep-UV resists and resolution enhancement techniques will be needed on top of this to obtain similar CD control.
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