Ms. Wan-Hsiang Liang Profile

Wan-Hsiang Liang

MTS Process Eng at GlobalFoundries

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Publications (1)

Proceedings Article | 19 March 2018 Presentation

The challenge of multi-patterning lithography for contact layer in 7nm and beyond (Conference Presentation)

Wan-Hsiang Liang, Guanchen He, Yuan Zhou, Ming Hao Tang, Bradley Morgenfeld, David Conklin

Proceedings Volume 10586, 105860B (2018) https://doi.org/10.1117/12.2297504

KEYWORDS: Lithography, Optical lithography, SRAF, Source mask optimization, Extreme ultraviolet, Photomasks, Etching, Optical proximity correction, Electroluminescence, Double patterning technology

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When technology node transitions to 14nm and beyond, multi-patterning technique including litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) with optical lithography is required to achieve device scaling until extreme ultraviolet (EUV) comes into full production. Although LELE and SADP are widely used and well-studied for line-space layers, the challenge of contact layers still remains unknown. In addition, process window (PW) and pattern defects are often characterized with lithography printability only before 7nm. However, when the gate length is pushed to the limitation of immersion lithography, hard mask open etch (HMO) also needs to be studied along with lithography printability to further optimize overall patterning process window (PW). In this paper, we first studied several optical proximity correction (OPC) techniques such as source-mask optimization (SMO) and sub-resolution assist features (SRAF) to improve PW. We then characterized the patterning PW on several patterning defects including single-layer bridging, multi-layer bridging, missing contact, unlanded contact, and extra contact by tuning develop CD (DCD) and HMO CD (MCD). SMO such as illumination source and projection lens wavefront has been extensively used to enlarge depth of focus (DoF). Two different XY polarizations sources were optimized via SMO and were verified on silicon based on overlap process window and mask error enhancement factor (MEEF). Both sources have achieved <90nm lithography PW and <3 MEEF for the selected SRAM and logic designs. The effect of SRAF size on patterning PW were studied by obtaining DoF and exposure latitude (EL) post develop and post HMO. DoF was enlarged by 20nm when increasing SRAF size; however, EL was reduced by 6% post develop and by 2% only post HMO, suggesting patterning PW should be studied at post HMO instead of post develop. When characterizing multi-patterning PW, two types of defects need to be considered: type 1) single-layer bridging and missing contact driven by lithography only; type 2) multi-layer bridging, unlanded contact, and extra pattern driven by both lithography and HMO. Type 1 defects were studied by lithography printability from focus-exposure matrix for different targets (dense/semi-iso/iso) and maximum lithography PW was achieved by adjusting DCD. Type 2 defects were studied by adjusting both DCD and MCD (etch bias). Missing contact was improved by 20x and unlanded contact was improve by 5x when DCD was increased by 8%; however, multi-layer bridging was worsen by 10x, which can be improved by decreasing MCD by 8%. As a result, overall patterning PW can only be obtained by combining lithography PW and HMO optimization.

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