Mr. Wansik Nam Profile

Wansik Nam

at SAMSUNG Electronics Co., Ltd.

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Proceedings Article | 26 May 2022 Poster + Presentation + Paper

Improved fab-out EDS prediction of memory device using effective accuracy equation

Heeyoon Han, Wansik Nam, Hyeungcheol Mun, Sangbong Lee, Sungyoon Ryu, Younghoon Sohn

Proceedings Volume 12053, 120531S (2022) https://doi.org/10.1117/12.2613619

KEYWORDS: Binary data, Metrology, Distortion, Semiconducting wafers, Semiconductors, Manufacturing, Data conversion, Data modeling, Yield improvement, Optics manufacturing

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In order to achieve pattern shrinkage of the memory device, the manufacturing process is getting more complicated and the production period is getting longer. Therefore, the methodology of predicting fab-out electrical die sorting (EDS) test results from in-fab metrology (CD, Optical CD, Thickness, etc.) data is becoming increasingly important. In this study, we propose a novel methodology to improve the fab-out EDS prediction of memory device with in-fab metrology data. Since fab-out EDS results of memory device are binary data consisting of pass or fail at the chip level, indices based on binary classification are suitable for verifying correlation between in-fab metrology data to fab-out EDS results. However, in memory device production, the number of pass chips is much larger than that of fail chips. So in this case, the data imbalance of the pass/fail chip ratio in memory semiconductor production can lead to distortion of binary classification indices such as accuracy, precision, recall, and F-score. We modified the accuracy equation of binary classification to compensate for distortion of binary classification indices due to data imbalance, allowing us to determine chip-level in-fab production specifications (specs) more accurately. We also confirm that the fab-out EDS prediction error has decreased 37.5% when using new in-fab production specs determined by our effective accuracy equation.

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