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Preliminary studies show that mask absorber sidewall angle (SWA) impacts pattern formation partially through aerial image asymmetries. The light and dark-side of the absorbers form a standing wave in the gap between them due to absorber side wall reflection and corner scattering. The absorbers’ standing waves further interact with the standing waves from the mask stack. Optimizing the absorber SWA is hypothesized to improve contrast thereby improving patterning robustness.
This study investigated the impact of absorber SWA on aerial image shape using simulation. The study was designed to understand if an optimal SWWA exists that improves patterning robustness in a manufacturing environment. CD, contrast, focus response, and other data were gathered and presented to understand the impact of SWA on patterning. From these simulated data, the possibility of an optimum SWA was explored.
Extreme ultraviolet mask multilayer material variation impact on horizontal to vertical pattern bias
This study explores the relationship between EUV mask stack reflectivity and horizontal to vertical pattern bias. In this computational study, the MoSi2 thickness is varied at systematic locations in the mask stack, then data on horizontal to vertical bias (H to V bias) for multiple features are gathered. The data will be used to understand the relationship between mask substrate reflectance, mask material thickness, and H to V bias. The study will also investigate the impact of high numerical aperture (0.55 NA anamorphic) imaging on the final H to V bias. Initial work indicates that a 1% variation in substrate reflectance results in approximately a 4% variation in CD.
Moreover, SEM emulation is applied for resist model calibration to capture subtle error signatures through dose and defocus. Finally, it should be noted that our SEM emulation methodology is based on the approximation of physical phenomena which are taking place in real SEM image formation. This approximation allows achieving better speed performance compared to a fully physical model.
We have successfully developed a triple patterning decomposition methodology that can effectively decompose an entire layout block or a chip. Formulating a triple patterning decomposition problem into a graph 3-color problem, the system first builds a graph to represent the layout. It then tries to reduce and partition the graph without changing its 3-colorability property. To color the reduced graph, we adopt a hybrid approach with a fast heuristic for coloring and an exact coloring algorithm for backup and conflict verification.
Unlike an odd cycle in double patterning, a triple patterning coloring conflict can’t be represented in a single loop. Another challenge for triple patterning is then how to report errors that the user can effectively use to fix them. For this purpose, minimum fix guidance – minimum to fix a conflict, and maximal minimum fix guidance – maximal choices are presented.
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