Proceedings Article | 10 December 2024
KEYWORDS: Metals, Source mask optimization, Lithography, Design rules, Design, Manufacturing, Semiconductors, Electroluminescence, SRAF, Industry
Over the past decade, the semiconductor industry has rapid development, fueled by Moore's Law. Concurrently, semiconductor manufacturing has consistently progressed, one of the prominent manifestations is the continuous reduction in pattern sizes and pitches. To accommodate these smaller pattern sizes, innovative techniques for enhancing lithography resolution have emerged, like off-axis illumination, Optical Proximity Correction (OPC), Phase Shift Mask (PSM), Source-Mask Co-Optimization (SMO), and so on, among others, each contributing significantly to achieving noteworthy outcomes. SMO, specifically, stands out by optimizing critical process parameters like Exposure Latitude (EL), Depth of Focus (DoF), and Mask Error Factor (MEF) for patterns governed by specific design rules. It accomplishes this by formulating a Cost Function, which, through SMO can significantly widens the process window for these patterns, ensuring compliance with manufacturing specifications. In this report, we studied the 7 nm node Back-End-Of-the-Line (BEOL) Metal layer’s process. Based on the definition of the design rules, the typical minimum pitch for this layer is 80 nm. We will select this minimum pitch for the patterns and combine it with other representative and characteristic patterns at this node to investigate the enhancement of SMO on the patterns at this technology node.
