Hotspot detection focused on lithography induced defects becomes crucial at advanced node due to the increasing complexity of the design and manufacture process. Compared with traditional lithography simulation techniques for hotspot detection, machine-learning-based methods have shown significant advantages attributing to the efficiency and generality of their model. However, most convolutional neural network-based hotspot detector can only inference a layout pattern at once. Therefore, sampling clip patterns from the detected layout is the bottleneck of the whole process and determines the performance of hotspot detection. We designed a flow to generate filter rules by clustering analysis of known hotspots, which can efficiently extract layout clips as detected samples to hotspot classifier. We further propose a feature parametric optimization method to extract valuable graphic features for classifiers and reduce redundancy from context patterns. Experimental results demonstrate that these techniques improve the accuracy of hotspots detection.
An optimized source has the ability to improve the process window during lithography in semiconductor manufacturing. Source optimization is always a key technique to improve printing performance. Conventionally, source optimization relies on mathematical–physical model calibration, which is computationally expensive and extremely time-consuming. Machine learning could learn from existing data, construct a prediction model, and speed up the whole process. We propose the first source optimization process based on autoencoder neural networks. The goal of this autoencoder-based process is to increase the speed of the source optimization process with high-quality imaging results. We also make additional technical efforts to improve the performance of our work, including data augmentation and batch normalization. Experimental results demonstrate that our autoencoder-based source optimization achieves about 105 × speed up with 4.67% compromise on depth of focus (DOF), when compared to conventional model-based source optimization method.
The effective test pattern is a crucial component for lithography process optimization such as Source Mask Optimization (SMO) and Optical Proximity Correction (OPC). The conventional parameterized test patterns cannot represent various contexts of patterns, thus sample patterns extracted from layout become an alternative option. This paper introduces a sample patterns extraction method based on the hierarchical clustering algorithm, according to the geometric characteristics. Meanwhile, an improved HLAC-based method is applied to the layout patterns at the stage of feature extraction for accurate characterization. The method can reduce the number of test patterns while maintaining high coverage of layout’s geometric features. The lithography process window is analyzed to validate the effectiveness of the patterns clustering flow. Moreover, the comparison between the spectrums of sample patterns and original layout also indicates that the proposed sampling method preserve a sufficient coverage of layout’s optical characteristics. Pattern extraction method in this paper could provide a candidate solution for fast test pattern generation with high coverage for lithography process exploration.
As the semiconductor industry enters 20 nm node and beyond, design restrictions and process complexity lay stress on the development for a new technology node. This paper introduces a hybrid hotspot library building method based on simultaneous optical and geometry analysis, which could help explore design rule optimization and enhance cycle time at early stage for new node development. Lithography simulation results verify the accuracy of this method. This method provide a feasible way to build up a preliminary Design Rule Checking (DRC) library even before process-freezing.
We demonstrate two different approaches of implementing design technology co-optimization (DTCO). One is on optimizing standard cells. Before being placed on mask, standard cells can be evaluated and optimized to gain better process windows. This approach enables an additional learning cycle before mask tapeout, reducing process development cost. The other approach uses a random pattern generator to create various patterns with high coverage based on given design rules. Lithography simulation is used to evaluate process window of these patterns, and annotates its printability. Test patterns generated in this way can be used for early process development.
This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.
Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.
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