3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap shows a decrease in the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to small values. In the W2W process, a wafer bonder is used to align and bond two whole wafers. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to ensure the copper pads line up properly before being bonded, driving an increased need for overlay metrology precision and die-bonder control. The bonded wafers are subsequently cut up into stacked chips using a dicing process and then undergo testing and further packaging. Advanced processing control (APC) for W2W hybrid bonding is an important factor in fulfilling the target on-product overlay (OPO) via litho inputs, in-plane distortion (IPD), overlay (OVL) and bonder correction knobs. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget.
Sub-2nm On Product Overlay (OPO), scribe line width reduction, and high-order scanner correctibles are driving innovative overlay (OVL) targets. One promising new imaging-based overlay (IBO) OVL target to address such challenging trends in multiple semiconductor segments is a small pitch AIM (sAIM). sAIM is in essence an IBO target with grating (previous layer) beside grating (current layer) which could be placed in a few layouts: square, rectangular, and Mosaic. In this work, we will present the sAIM operational concept and performance including Total Measurement Uncertainty (TMU), residuals, and accuracy (ADI on-target offset vs. ACI on-device or target), which is often referred to as Non-Zero Offset (NZO).
Advanced semiconductor devices target sub-2nm on-product overlay (OPO) and manufacturers utilize dense overlay (OVL) sampling and non-zero offset (NZO) control to enable such strict performance. Accurate optical OVL metrology systems with fast move-and-measurement (MAM) utilized at the after-develop inspection (ADI) step are required to support this OPO trend. This work presents an innovative Artificial Intelligence (AI) based, ultra-high-speed, overlay target focusing and centering approach on imaging-based overlay (IBO) measurements in the ADI step. The algorithm uses pre-trained image features and a deep learning model. The algorithm allows the measurement of every site across the wafer in its best centering and contrast focus position and thus overcomes intra-wafer process variations and enhanced measurement accuracy. The data will include results from multi-lot advanced DRAM process with basic performance analysis such as total measurement uncertainty (TMU), tool-to-tool matching (TTTM) and additional key performance indicators (KPIs).
3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek to gain higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap strives to reduce the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to 10μm and below. In the W2W process, a wafer bonder is used to align and bond two whole wafers. The bonded wafers are then cut up into stacked chips using a dicing process and undergo testing and further packaging. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to make sure the copper pads to be bonded line up perfectly, driving an increased need for overlay metrology precision and die-bonder control. Overlay metrology challenges include thick silicon and tight overlay (OVL) error specifications to enable tight and fast on-product overlay (OPO) control for 3D NAND product development. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget, accuracy, measurability, robustness, and throughput.
With the continuous shrinking of semiconductor device nodes, the reduction of on-product overlay (OPO) becomes extremely critical for high-yield IC (Integrated Circuit) manufacturing. This requires accurate overlay (OVL) process control which can be better achieved by using an optimized OVL target design and a more advanced metrology platform. The novel rAIM® imaging-based-overlay (IBO) target, which has a grating-over-grating structure with significantly smaller pitch sizes as compared to the standard advanced-imaging-metrology (AIM®) target, can improve OVL measurement accuracy by adopting a more device-compatible design with high Moiré sensitivity. This paper demonstrates the advantages of rAIM targets by comparing and quantifying their performance to standard AIM targets through key parameters including raw OVL, residuals, precision, and total measurement uncertainty (TMU). We also present the performance of rAIM targets on different OVL metrology platforms. We conclude that with an optimized target design and an advanced OVL measurement platform, rAIM targets can be an ideal overlay metrology solution for advanced dynamic random-access memory (DRAM) devices.
The semiconductor industry continually evaluates new materials to improve the process or minimize product variability, which could create measurement challenges for metrology tools in the visible and near-infrared (NIR) spectrum. Opaque materials (i.e., ‘hard masks,’ ‘HM’) are placed in between the resist (i.e., inner layer) and process (i.e., outer layer or underlying layer) in 3D NAND or DRAM processes to control the etch of high aspect-ratio structures to maximize product yield. However, longer wavelengths (e.g., IR WL) may be required to penetrate and properly view the underlying process layer and measure OVL accurately. In this work, longer wavelengths will be evaluated to improve measurement accuracy and keep up with the increasing use of opaque materials, which is expected to increase in future nodes. We will review the benefits of IR WL to OVL measurement accuracy by quantifying the OVL residuals, contrast precision (CP), and total measurement uncertainty (TMU) on multiple DRAM and 3D NAND critical layers.
3D heterogeneous integration is an evolving segment of the world semiconductor industry roadmap to enable improvements in device performance beyond Moore’s law expectations. These “More than Moore” (MtM) performance enhancements have the potential for realizing dramatic improvements in communication bandwidth, design flexibility that enables new system architectures on-chip or at the wafer level, and overall cost reduction. 3D heterogeneous integration strives to increase electrical connectivity through pitch and contact dimensional scaling to enable <10μm pitch solder bump scaling, and sub-micrometer hybrid Cu/dielectric fusion bond connectivity. Integration options include wafer to wafer (W2W), pick-and-place (P&P), and die to wafer (D2W) assembly strategies. Enhanced process capability and systems architecture imposes new overlay (OVL) metrology challenges to address variable silicon substrate thickness, stressinduced wafer or die distortions, and tight OVL error specifications. In this work, we will cover the OVL trends and challenges surrounding this evolving segment. We will cover different OVL aspects such as accuracy, measurability, reproducibility, and throughput and discuss their impact on pre and post-bonding error budgets.
In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer™ OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.
Over the past few years, on product overlay (OPO) challenges have become serious yield limiters for the latest technology nodes, requiring new and innovative overlay (OVL) metrology solutions. OVL metrology systems must have excellent measurability capabilities to cover as many different layers as possible, minimize any systematic contribution to measured OVL and demonstrate low residuals and high correlation to AEI SEM and AEI in die overlay (IDO). OVL metrology system manufacturers are required to introduce new target designs, tool hardware (HW) and advanced algorithms to keep up with said challenges. The paper will present optical OVL solutions per segment: foundry, logic, DRAM, and 3D NAND. We will review various new technologies developed in the last year that improve the OVL measurement systems’ performance to meet the above challenges. We will see how the new innovative targets improve measurability and accuracy on imaging-based overlay (IBO) and scatterometry-based overlay (SCOL®). Then, we will review new hardware components designed to improve measurability and overall fleet matching. Lastly, we will discuss how advanced machine learning (ML), multi-wavelength (MWL) and signal-weighting algorithms improve measurability, accuracy, and overall measurement performance.
We show that an overlay (OVL) metrology system based on a scanning electron microscope can achieve accurate registration of buried and resist (top) structures. The positions were determined by both Back Scattered Electrons (BSE) and Secondary Electrons (SE). The accuracy was quantified for After-Development Inspection (ADI) of an advanced EUVL process. Results by linear tracking showed accuracy below 0.4nm, robust across process variation and target designs. The influence of various measurement conditions, e.g. Field of View, on position and OVL tracking was negligible. The measurement methodology presented is applicable for both standalone High Voltage SEM (HV-SEM) registration targets and optical targets, such as the Advanced Imaging Metrology (AIM®) target used by Imaging Based Overlay (IBO) metrology systems. Using SEM ADI OVL results as a calibration for optical overlay metrology tools we can demonstrate significant improvements in the optical ADI OVL accuracy on small targets like AIM in-die (AIMid).
On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.
As 3D NAND devices increase memory density by adding layers, scaling and increasing bits-per-cell, new overlay (OVL) metrology challenges arise. On product overlay (OPO) may decrease for critical thick layers such as thick deck-to-deck alignment, whereas high aspect ratio (Z-axis) structures introduce stress, tilt and deformation that require accurate and robust OVL measurements. Advanced imaging metrology (AIM®) targets, that consist of two side-byside periodic gratings in the previous and current layers, are typically used to measure OVL with Imaging Based Overlay (IBO) metrology systems. In this paper, we present a new approach that utilizes the Talbot effect in AIM to produce multiple contrast planes along the Z-axis, which enables a common focus position for both layers at a similar focus plane, resulting in improved measurement robustness. We will present Talbot effect theory, target design steps by metrology target design (MTD) simulator, actual measurement results on an advanced 3D NAND device and conclusions for such targets.
In the latest 3D NAND devices there is a larger focus on measurement accuracy control, coupled with more traditional minimization of Total Measurement Uncertainty (TMU). Measurement inaccuracy consumes an increasingly significant part of the overlay (OVL) budget, requiring control and optimization.
In this paper we will show the improvement in imaging OVL measurement accuracy using wave tuning (WT) capability combined with advanced algorithms to address 3D NAND process challenges. In addition to new OVL target designs that take advantage of WT capability, we also demonstrate improvement in OVL model residuals through optimization of measurement bandwidth, focus position and number of grab frames. Improvements in precision and tool-to-tool matching are also realized through both optimization of the region of interest (ROI) and splitting measurement areas using a dual-recipe technique.
Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.
KEYWORDS: Metrology, Optical parametric oscillators, Optical design, Overlay metrology, 3D acquisition, 3D metrology, Integrated circuits, Manufacturing, Logic, Process control
On product overlay (OPO) shrink is a key enabler to achieve high yield in integrated circuit manufacturing. One of the key factors to enable accurate measurement on grid (target) is the use of optimized overlay (OVL) mark design to achieve low OPO. The OVL mark design enables accurate and robust OVL metrology and improves measurability and basic performance requirements such as total measurement uncertainty (TMU). In this paper, we demonstrate the methodology of mark design for different devices based on simulations, measurements and verification. We compare OVL performance of AIM® targets and grating-over-grating imaging targets utilizing the Moiré effect. Methodologies described in this work utilize robust AIM (rAIM™) targets, target design from the MTD AcuRate™ simulation-based OVL metrology target design tool, and the Archer™ OVL metrology system.
For today’s advanced processes, in order to achieve higher optical lithography resolution, some of the layers require extreme dipole illumination conditions. One example is the modern DRAM process, where numerous critical layers are patterned with extreme dipole scanner illumination. Conventional (both imaging-based and diffraction-based) overlay marks on such layers typically use horizontal or vertical lines that suffer from insufficient accuracy in overlay device tracking. The new Diagonal AIM (DAIM™) overlay mark mimics the actual device through the usage of tilted structures. Significant improvement in device overlay tracking was demonstrated using the DAIM overlay mark.
On product overlay (OPO) challenges are quickly becoming yield limiters for the latest technology nodes, requiring new and innovative metrology solutions. In this paper we will cover current and future overlay trends in logic and memory device processing. We will review new lithography overlay challenges and node-after-node trends in the OPO error budget for advanced logic, DRAM, and 3D NAND devices. The central question of this paper is whether optical overlay metrology can keep up with challenges that include accuracy, intra-field variability, target-to-device offset, and others. After surveying the two dominant technologies in optical overlay metrology (IBO and SCOL®), we will outline innovative solutions that will help to address metrology challenges for the new device nodes.
This paper presents multispectral active gated imaging in relation to the transportation and security fields. Active gated imaging is based on a fast gated camera and pulsed illuminator, synchronized in the time domain to provide range based images. We have developed a multispectral pattern deposited on a gated CMOS Image Sensor (CIS) with a pulsed Near Infrared VCSEL module. This paper will cover the component-level description of the multispectral gated CIS including the camera and illuminator units. Furthermore, the design considerations and characterization results of the spectral filters are presented together with a newly developed image processing method.
KEYWORDS: Imaging systems, Image sensors, Near infrared, Sensors, Cameras, Fiber optic illuminators, Gated imaging, Safety, Night vision, Control systems
The paper presents the Active Gated Imaging System (AGIS), in relation to the automotive field. AGIS is based on a fast gated-camera equipped with a unique Gated-CMOS sensor, and a pulsed Illuminator, synchronized in the time domain to record images of a certain range of interest which are then processed by computer vision real-time algorithms. In recent years we have learned the system parameters which are most beneficial to night-time driving in terms of; field of view, illumination profile, resolution and processing power. AGIS provides also day-time imaging with additional capabilities, which enhances computer vision safety applications. AGIS provides an excellent candidate for camera-based Advanced Driver Assistance Systems (ADAS) and the path for autonomous driving, in the future, based on its outstanding low/high light-level, harsh weather conditions capabilities and 3D potential growth capabilities.
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