This paper focuses on the application of photolithography, a widely adopted microfabrication technique, in the creation of SRG display. While photolithography is a well-established process, there exist notable challenges in utilizing it for SRG display manufacturing. This work addresses key concerns such as optical proximity correction (OPC), photomask quality, lithography materials, and optimal process conditions for achieving desirable waveguide performance. Moreover, this paper draws a comparison between the patterning requirements and differences in conventional semiconductor lithography and the lithography applied to AR display manufacture. By presenting an in-depth analysis of the intricacies associated with photolithography-based SRG display fabrication, this work aims to provide valuable insights into overcoming technical hurdles and enhancing the overall quality and efficiency of AR waveguide displays.
KEYWORDS: Etching, Extreme ultraviolet, Line edge roughness, Optical lithography, Line width roughness, Silicon, Double patterning technology, Dielectrics, Metals, System on a chip
We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nm immersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.
Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask has to scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques [1]. This paper provides further understanding of this class of materials from a fundamental point of view. We first propose a hypothesis of the adhesion mechanism, and probe key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect the printing performance. We then conduct a systematic study to understand printing capability at various pitches for different silicon-based substrates. By comparing the process window, we gain comprehensive understanding of the printing limits and failing modes with this approach. We provide a comparative study of a grafted adhesion layer vs. a conventional spin on BARC type material, including defectivity. Pattern transfer to hard mask with varied etch chemistry is conducted to understand the performance of polymer brush during etch.
We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.
Extending extreme ultraviolet (EUV) single exposure patterning to its limits requires more than photoresist development. The hardmask film is a key contributor in the patterning stack that offers opportunities to enhance lithographic process window, increase pattern transfer efficiency, and decrease defectivity when utilizing very thin film stacks. This paper introduces the development of amorphous silicon (a-Si) deposited through physical vapor deposited (PVD) as an alternative to a silicon ARC (SiARC) or silicon-oxide-type EUV hardmasks in a typical trilayer patterning scheme. PVD offers benefits such as lower deposition temperature, and higher purity, compared to conventional chemical vapor deposition (CVD) techniques. In this work, sub-36nm pitch line-space features were resolved with a positive-tone organic chemically-amplified resist directly patterned on PVD a-Si, without an adhesion promotion layer and without pattern collapse. Pattern transfer into the underlying hardmask stack was demonstrated, allowing an evaluation of patterning metrics related to resolution, pattern transfer fidelity, and film defectivity for PVD a-Si compared to a conventional tri-layer patterning scheme. Etch selectivity and the scalability of PVD a-Si to reduce the aspect ratio of the patterning stack will also be discussed.
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the full scaling entitlement of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity and LWR/LER must be improved in terms of patterning performance. Tokyo Electron Limited (TEL™) and IBM Corporation are continuously developing manufacturing quality processes for EUV. In this paper, we review the ongoing progress in coater/developer based processes (coating, developing, baking) that are required to enable EUV patterning.
In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.
We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
In this paper we will describe the development of a new 12% high transmission phase shift mask technology for use
with the 10 nm logic node. The primary motivation for this work was to improve the lithographic process window for
10 nm node via hole patterning by reducing the MEEF and improving the depth of focus (DOF). First, the simulated
MEEF and DOF data will be compared between the 6% and high T PSM masks with the transmission of high T mask
blank varying from 12% to 20%. This resulted in selection of a 12% transmission phase shift mask. As part of this
work a new 12% attenuated phase shift mask blank was developed. A detailed description and results of the key
performance metrics of the new mask blank including radiation durability, dry etch properties, film thickness, defect
repair, and defect inspection will be shared. In addition, typical mask critical dimension uniformity and mask minimum
feature size performance for 10 nm logic node via level mask patterns will be shown. Furthermore, the results of work
to optimize the chrome hard mask film properties to meet the final mask minimum feature size requirements will be
shared. Lastly, the key results of detailed lithographic performance comparisons of the process of record 6% and new
12% phase shift masks on wafer will be described. The 12% High T blank shows significantly better MEEF and larger
DOF than those of 6% PSM mask blank, which is consistent with our simulation data.
Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.
In this paper, we discuss the lithographic qualification of high transmission (High T) mask for Via and contact hole applications in 10nm node and beyond. First, the simulated MEEF and depth of focus (DoF) data are compared between the 6% and High T attnPSM masks with the transmission of High T mask blank varying from 12% to 20%. The 12% High T blank shows significantly better MEEF and larger DoF than those of 6% attnPSM mask blank, which are consistent with our wafer data. However, the simulations show no obvious advantage in MEEF and DoF when the blank transmittance is larger than 12%. From our wafer data, it has been seen that the common process window from High T mask is 40nm bigger than that from the 6% attnPSM mask. In the elongated bar structure with smaller aspect ratio, 1.26, the 12% High T mask shows significantly less develop CD pull back in the major direction. Compared to the High T mask, the optimized new illumination condition for 6% attnPSM shows limited improvement in MEEF and the DoF through pitch. In addition, by using the High T mask blank, we have also investigated the SRAF printing, side lobe printing and the resist profile through cross sections, and no patterning risk has been found for manufacturing. As part of this work new 12% High T mask blank materials and processes were developed, and a brief overview of key mask technology development results have been shared. Overall, it is concluded that the High T mask, 12% transmission, provides the most robust and extendable lithographic solution for 10nm node and beyond.
The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
The printing of contact holes using positive tone development typically requires the interference of more than the 0th and 1st diffracted orders. In the 2d case and cQuad illumination in a positive tone process, if (0,0), (±1,0), and (0,±1) are exclusively present, the relevant contrast for imaging can in the best case not rise above 0.33, which is typically insufficient for a good process window. And this maximum value can only be achieved if the (0,0) and (±1,0) orders are matched to give a perfect sine wave of perfect contrast in y while the (0,0) and (0,±1) orders yield perfect contrast in x. In reality, the contrast is quite a bit lower. On the other hand, for negative tone development we are interested in the minima of the intensity–the dark locations in the image–and if we can manage to reduce the intensity in the minima we can achieve a high contrast image. Through a choice of RET and illumination, we manage to achieve a resolution for contact holes in 2d at k1 values that can otherwise be achieved only for 1d imaging.
Earlier work has been done on double exposures that exposed in the same resist a horizontal grating with x-dipoles and subsequently a vertical grating with y dipoles, without intermediate process steps. This yielded a high contrast image in resist at k1 <0.3.1 We show that an equivalent result can be achieved in a single exposure with a single mask, at admittedly high dose. We investigate the process parameters and the related mask tolerances, and find a non-intuitive result for the mask pattern that yields an optimized image at given mask specifications. Finally, we investigate the extension of this technique to EUV through simulations and experiments.
We have performed a systematic study regarding the diblock composition to keep the size of the cylinders relatively constant despite the shape of the guiding pattern. We have also explored how some guiding patterns shapes provide acceptable cylindrical assembly using an EUV exposure system. This study assumes that LER is a random phenomenon which conformably follows the shape of the guiding pattern. While the edges of the guiding pattern have fluctuations related to the LER of the EUV resist, as long as the centroid of the guiding pattern remains constant, the rectification characteristics of DSA permits adequate hole formation. In this paper we include the level of LER a guiding pattern can exhibit given a pre-determined diblock copolymer / homopolymer mixture. As the amount of homopolymer increases, the size and placement of the assembled diblock becomes less sensitive to the guiding pattern’s edge roughness. This study also explores how the addition of homopolymer is only effective up to a point, as a homopolymer-rich blend is not able to assemble properly. One of the concerns about homopolymer-rich mixtures is the effect it has in the formation of defects. Such effect has not been fully characterized but this study serves as the basis for testing optimal combinations of materials and lithography settings for an EUV system, with the end goal to enable contact/via printing at lower EUV source power requirements.
The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for
Excellence in July marked the transition from research to process development using EUV lithography. Early process
development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and
process capability. This work highlights some key learning from early EUV process development with a focus on
identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV
scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical
dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line
width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing.
While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately
evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built
from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational
lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these
irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern
characterization.
The objective of this work is to describe the advances in 193nm photoresists using negative tone
developer and key challenges associated with 20nm and beyond technology nodes.
Unlike positive tone resists which use protected polymer as the etch block, negative tone
developer resists must adhere to a substrate with a deprotected polymer matrix; this poses
adhesion and bonding challenges for this new patterning technology. This problem can be
addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in
them (SiARC), which are specifically tailored for compatibility with the solvent developing
resist. We characterized these modified SiARC materials and found improvement in pattern
collapse thru-pitches down to 100nm.
Fundamental studies were carried out to understand the interactions between the resist materials
and the developers. Different types of developers were evaluated and the best candidate was
down selected for contact holes and line space applications. The negative tone developer
proximity behavior has been investigated through optical proximity correction (OPC)
verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to
less than 100 adders/wafer by optimizing the develop process. Electric yield test has been
conducted and compared between positive tone and negative tone developer strategies. In
addition, we have done extensive experimental work to reduce negative tone developer volume
per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of
positive tone CoO.
In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental
materials/process interaction perspective. Several key differences exist between a negative tone develop
process and a traditional positive tone develop system. For example, the organic solvent dissolves the
unexposed material, while the deprotected resist remains intact. This causes key differences in key
patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity.
We have carried out fundamental studies to understand these new interactions between developer and
remaining resist with negative tone develop systems. We have characterized the dynamic dissolution
behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent
developers. We have also compared contrast curves, and a fundamental model of image collapse. In
addition, we present first results on Optical Proximity Correction (OPC) modeling results of current
Negative Tone Develop (NTD) resist/developer systems.
With 22nm logic node arriving prior to EUV implementation, alternative immersion optical lithographic processes
are required to drive down to smaller feature sizes. There is an ongoing effort to examine the application of the negative
tone imaging (NTI) process for current and future nodes. Although NTI has previously shown difficulties with respect to
swelling, high chemical reactivity with oxygen, and the need for special equipment needed for the solvent-based
development, NTI photoresists (PR) typically exhibit stronger adhesion to silicon than that of positive tone photoresists
(a characteristic that helps mitigate pattern collapse). We will provide suggestions on how to improve the image quality,
as well as the resulting defectivity, for desired geometries. This paper will primarily focus on the full litho process
optimization and demonstrate repeatable, and manufacturable critical dimension uniformity (CDU), and defectivity
optimization for trench and via structures.
In order to create three-dimensional (3D) photonic crystals (PCs) with large photonic bandgap properties (PBG), it is
necessary to control the 3D fabrication with desired symmetry, high index contrast, and high structural stability. To
rational design the 3D photonic structures fabricated by holographic lithography, we have conducted quantitative
analysis to study structural distortion during each processing step and their impact to PBG. Because of the relatively low
dielectric contrast between typical polymers and air, the directly patterned polymer structures are usually used as
templates for backfilling of high-index materials, followed by removal of the polymer template to realize complete
PBGs. Therefore, the fidelity of the final PCs is critically dependent on the thermal and mechanical robustness of the
polymer templates, the deposition methods (e.g. dry chemical vapor deposition vs. wet chemistry), and the template
removal procedure. Here, we address these challenges using different photoresist systems and deposition methods to
create Si and titania 3D PCs.
Diamond-like silicon photonic crystals were fabricated by sequential chemical vapor deposition of silica and silicon on
polymer templates photopatterned by holographic lithography. The optical properties of the 3D crystals after each
processing step were measured and compared to the corresponding bandgap simulation. The core-shell morphology
formed during CVD process is approximated using two level surfaces.
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