As technology nodes shrink and layout sizes grow, layout pattern matching in lithography defect detection becomes increasingly time-consuming. To address this, we propose a fast layout pattern matching algorithm based on spatial indexing. The method first uses geometric information to locate potential matching regions, then employs spatial indexing to divide the layout into sub-regions, quickly excluding irrelevant areas and improving efficiency. Multithreading and compiler optimizations further enhance speed. Experiments show that our approach achieves a 20- 30x speedup over commercial tools while maintaining 100% accuracy, demonstrating its effectiveness for very large-scale integrated circuit defect detection.
The critical dimension scanning electron microscope (CDSEM) plays an essential role in measuring sub-nanometer scale patterns after lithography and etching process. However, its measurement capabilities are limited, making it difficult to accurately measure complex pattern such as tip-to-tip or tip to side structures. Additionally, it’s very challenging for CDSEM to perform an accurate multiple-layer multiple-process data measurement and process characterization, such as etch bias and channel length/width uniformity. This paper addresses these challenges by performing SEM contours extraction and data analysis on the gate (GT) and active area (AA) stacking structures of Static Random Access Memory (SRAM) bit cell pattern. Utilizing SIEMENS EDA's Calibre SEMSuite and Calibre OPCVerify tools, we extracted contours from SEM images to analyze process variations at the center, middle, and edge positions of the wafer. By overlaying the contours of ADI and AEI, we determined the etch bias across the entire SRAM bit cell pattern. Additionally, by overlaying the contours of AA and GT, we ascertain the channel width and length (W/L) value of the transistors. This data provides a direction for optimizing SRAM layout design and establishes a systematic method for silicon data analysis.
There are many kinds of OPC test pattern in Contact (CT) layer, and different measurement methods are used to measure the model data, resulting in a large simulation error of y-direction rectangle type patterns in the model. We propose a new method to build OPC model of CT layer by using SEM image contour. In this work, the SEM image contour was extracted by Calibre SEMSuite™, and the measurements of the corresponding test pattern was calculated according to the image contour. The CD-SEM (critical dimension scanning electron microscope) measurement data of anchor point was used to calibrate the modeling data and then the OPC model was built. Compared with the model tuned by CD measurements, the simulation error of y-direction rectangle type patterns caused by measurement method is effectively reduced. Our experiments show that it is feasible to build a high precision OPC model of CT layer by using this method.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.