The calibration of optical proximity correction (OPC) models has become increasingly challenging, especially when the behavior of photoresist on wafers cannot be adequately interpreted using conventional model terms assembled in a linear fashion. Additionally, fine-tuning such linearly separable physical components proves difficult due to evidence of nonlinear interactions among physical effects. In this study, we propose leveraging an advanced regression technique that progressively augments the linear model assembly with perturbative nonlinear neural network units the sharing same set of physics-inspired model terms as its base model, aiming to enhance model accuracy while maintaining stability. The research approach involves setting up initial models using conventional model calibration techniques, including optical model optimization and resist model optimization. Subsequently, we incorporate the Synopsys Advanced Regression (AR) neural network to identify essential non-linear interactions among modeling components. We selectively include these non-linear components into the existing linear model to capture on-wafer behavior. The entire process is designed to integrate seamlessly into the existing OPC production flow, ensuring a balance between model accuracy and efficiency. To evaluate the efficacy of the Synopsys AR method, we conduct tests on layers from 3D-NAND. The results demonstrate that this approach significantly reduces calibration costs due to its simpler calibration requirements.
Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern [1]. When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.
We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
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