For Extreme Ultra-violet Lithography (EUVL) targeting at 11nm and beyond design rules, the minimum printable
EUVL multilayer (ML) mask defect size can be as small as 20-25nm. As a result, the defect-free EUVL ML mask blank
fabrication remains the top challenge for EUVL mask. Aspects of this challenge include high quality blank substrate
material (low thermal expansion material) fabrication, substrate polishing, substrate cleaning, blank handling, ML
deposition, and high sensitivity substrate and blank defect inspection. High investment cost and potential low blank yield
due to stringent defect-free requirement can quickly drive up EUVL cost of ownership. It is anticipated, however, the
EUVL ML blank yield can be drastically improved if we can allow a few defects on a ML blank. Utilizing such a
"defective" grade mask blank to fabricate a defect-free EUVL mask requires several defect mitigation schemes during
mask patterning processes. These schemes include modifying mask absorber pattern via repair tool to compensate the
effect of an adjacent ML defect and using absorber pattern to cover the ML defects. In this paper, we focused on the
study and demonstration of using device pattern to cover limited number of blank defects. The steps of this defect
mitigation process include blank fiducial mark patterning, defect location relative to fiducial mark precision
measurement, automated pattern shift solution simulation for a given ML defect map, and precision alignment of the
device pattern to the blank defects during e-beam write. With these steps, we have successfully demonstrated the
coverage of several targeted ML blank defects simultaneously via global device pattern shift.
With each new process technology node, chip designs increase in complexity and size, leading to a steady
increase in data volumes. As a result, mask data prep flows require more computing resources to maintain
the desired turn-around time (TAT) at a low cost. The effect is aggravated by the fact that a mask house
operates a variety of equipment for mask writing, inspection and metrology - all of which, until now,
require specific data formatting. An industry initiative sponsored by SEMI® has established new public
formats - OASIS® (P39) for general layouts and OASIS.MASK (P44) for mask manufacturing equipment -
that allow for the smallest possible representation of data for various applications. This paper will review a
mask data preparation process for mask inspection based on the OASIS formats that also reads
OASIS.MASK files directly in real time into the inspection tool. An implementation based on standard
parallelized computer hardware will be described and characterized as demonstrating throughputs required
for the 45nm and 32nm technology nodes. An inspection test case will also be reviewed.
KEYWORDS: Line edge roughness, Photomasks, Semiconducting wafers, Line width roughness, Scanning electron microscopy, Spatial frequencies, Light sources, Wafer-level optics, Fourier transforms, Decision support systems
Contribution of mask line edge roughness (LER) to resist LER on wafers was studied both by simulations and experiments. LER transfer function (LTF) introduced by Naulleau and Gallatin was generalized to include the effect of mask error enhancement factor (MEEF). Low spatial frequency part of LTF was enhanced by MEEF while high spatial frequency part was suppressed due to the numerical aperture limit of a stepper. Our model was experimentally verified as follows. First LER of a mask was measured by a scanning electron microscope. Then the mask LER was multiplied by LTF to simulate the aerial image LER on wafers. It was confirmed that the simulated LER agreed well with the LER measured by AIMSTM. Based on our model the contribution of the mask LER to the resist LER on wafers was estimated. According to our estimation the requirement of the mask LER should be as tight as that of the resist LER on wafers.
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