Low track height standard cell design in iN7 using scaling boosters

S. M. Y. Sherazi; C. Jha; D. Rodopoulos; P. Debacker; B. Chava; L. Matti; M. G. Bardon; P. Schuddinck; P. Raghavan; V. Gerousis; A. Spessot; D. Verkest; A. Mocuta; R. H. Kim; J. Ryckaert

doi:10.1117/12.2257658

4 April 2017 Low track height standard cell design in iN7 using scaling boosters

S. M. Y. Sherazi, C. Jha, D. Rodopoulos, P. Debacker, B. Chava, L. Matti, M. G. Bardon, P. Schuddinck, P. Raghavan, V. Gerousis, A. Spessot, D. Verkest, A. Mocuta, R. H. Kim, J. Ryckaert

Author Affiliations +

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 101480Y (2017) https://doi.org/10.1117/12.2257658
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Citation Download Citation

S. M. Y. Sherazi, C. Jha, D. Rodopoulos, P. Debacker, B. Chava, L. Matti, M. G. Bardon, P. Schuddinck, P. Raghavan, V. Gerousis, A. Spessot, D. Verkest, A. Mocuta, R. H. Kim, and J. Ryckaert "Low track height standard cell design in iN7 using scaling boosters", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480Y (4 April 2017); https://doi.org/10.1117/12.2257658

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