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Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing
Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers.
In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.
At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff performance, power, area and manufacturability. However, implementation platforms don’t typically have access to process information and process teams don’t have design knowledge, and optimization loops required for Design-Technology-Co-Optimization (DTCO) are either impossible or at best long and expensive for fabless design house.
Joining forces, ASML, IMEC and Cadence Design Systems developed an In-design and signoff lithography physical analysis well suited for 7/5nm and below. The Tachyon OPC+ engine used by IMEC 7/5nm process has been integrated in Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process models, recipes, and hotspot detectors. This flow leverages existing LPA infrastructure for both custom and digital design platforms, as well as standalone signoff.
Depending upon the end application, LPA could be launched either from place & route or custom layout or standalone. LPA processes first the design database to identify hierarchy, decompose the layout for coloring and apply pattern matching to identify location requiring simulation. The layout is then passed to the Tachyon OPC tool to perform optical process correction and model-based litho verification that is validated on Silicon. The hotspots and contours are processed by LPA for generation of hotspot marker and fixing guidelines and provide all this information to the design environment.
The flow has been developed and demonstrated to work on IMEC 7nm, and can be ported to smaller or larger technologies. The paper will present the result of this In-design and signoff lithography physical analysis flow, how DTCO and design teams can add manufacturability to PPA.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches2,3. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option.
We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.
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