Novel fast multiplier implemented using FPGA

Janusz Jabłoński; Marek Węgrzyn

doi:10.1117/12.2206018

11 September 2015 Novel fast multiplier implemented using FPGA

Janusz Jabłoński, Marek Węgrzyn

Proceedings Volume 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015; 96623Z (2015) https://doi.org/10.1117/12.2206018
Event: XXXVI Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (Wilga 2015), 2015, Wilga, Poland

Abstract

In the paper, the solution dedicated for FPGA devices of a synthesis of parallel multiplication systems with the alternative approach, called mutual exclusion, for results of partial products is presented. There are proposed a reducer with the factor 4:2 for parallel multipliers, based on Wallace tree structures, that are dedicated for 4-input and 1-output Look-Up Table (LUT) function generator used in FPGA devices. The elaboration refers to the solution for multiplying using FPGAs the numbers of 4 and 8 bits. However it can be enlarged up to 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service - fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.

Citation Download Citation

Janusz Jabłoński and Marek Węgrzyn "Novel fast multiplier implemented using FPGA", Proc. SPIE 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 96623Z (11 September 2015); https://doi.org/10.1117/12.2206018

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