2.1

The practical era

Successful application of lithography to semiconductor processing required that a number of practical problems first be solved. This will be illustrated by two examples. The first example involves a well-known phenomenon that is addressed in the processing of photoresist, that of edge-bead, where a thick ring of resist is created at the edges of wafers when resist is spin-coated. This edge-bead can be problematic, leading to defects and focus issues if not removed. Consequently, special techniques have been developed for removing the edge-bead.¹ In the early days of semiconductor lithography, the edge-bead was large. During investigations into the impact of the shape of the wafer edge on edge-bead it was found that beveled wafer edges resulted in smaller edge-bead.² Moreover, it was also found with beveling that the elimination of the sharp corner at the wafer edge resulted in significantly reduced wafer breakage, providing additional motivation for beveling wafers at the edge.

Another practical problem addressed several decades ago was related to adhesion promotion. Hexamethyldisilazane (HMDS) had long been used to promote the adhesion of photoresist. Initially, HMDS was applied in liquid form to wafers immediately prior to resist coating. The HMDS was somewhat effective at displacing the water physisorbed on the wafer surface, but only partially so. An improved adhesion promotion process, needed for ensuring adhesion of the smaller features that were being patterned as a result of scaling, consisted of first heating the wafers in a vacuum to drive off the water, and then introducing the HMDS in vapor form. Initially, vapor priming was a batch process, with cassettes of wafers placed into ovens. (Fig. 3.) Later this technique was adapted for integration into wafer track processing tools. The vapor prime process had several advantages over the prior application of HMDS in liquid form. First, the increased degree of water displacement improved the efficacy of adhesion promotion, which became necessary as feature sizes became smaller. The application of HMDS in vapor rather than liquid form resulted in fewer defects, and it reduced chemical consumption.

Figure 3.

A vapor prime oven from Yield Engineering Systems.³

2.2

Early modeling and simulation

A significant advance in lithographic technology occurred when theoretical simulations were introduced, starting with a model created for characterizing positive resist photochemistry by Dill and co-workers.⁴ This was followed by the creation of SAMPLE, which was an early computer program for simulating projection lithography.⁵ SAMPLE was accessible by many lithographers, enabling the widespread use of simulation for understanding problems in lithography.The power of simulation was manifested early. For example, there had long been speculation that optical lithography would be limited by depth-of-focus and would need replacement by other lithographic technologies, such as x-ray or ebeam lithography. Early simulations showed that optical lithography was quite extensible by use of shorter optical wavelengths and practical increases in numerical aperture.⁶ Early exposures using shorter wavelengths did not provide as much improvement in resolution as expected from consideration of optical images, but application of the Dill model revealed the need to optimize resist optical parameters.⁷ Building on the foundation established with SAMPLE, additional simulation programs became available, increasing further the application of modeling and simulation for understanding and solving problems in lithography.⁸

Thin film interference effects and high reflection from substrates coated with aluminum films were problems for early stepper lithography. (Fig. 4) SAMPLE and other early simulation software could be used to predict standing waves and other manifestations of substrate reflections, but often merely the application of simple equations enabled the identification of solutions to problems resulting from reflections from the substrate.⁹ As simple as this modeling was, it differed from the earlier era of lithography, in which few equations would appear in papers on lithography.

Figure 4.

(a) Micrograph of a pattern after etch. The feature was patterned using an 0.3 NA g-line stepper. The arrows show region where the linewidth varies considerably across the length of the feature, a consequence of thin film optical effects. (b) Schematic cross section of the region indicated by arrows in (a). Because of the variations in thin film thicknesses, the reflections from the substrate varied considerably, leading to the poor patterning indicated in (a).

In keeping with the increased focus on numerical calculations, process monitoring also became more quantitative. Early process control monitors were often of a pass/fail nature, and sometimes involved only visual inspection of monitor structures, rather than parametric measurement. This situation changed rapidly, and there was sufficient interest in measurements that a stand-alone metrology conference was added to the SPIE Advanced Lithography Symposium in 1987. Quantitative measurements were critical for improvements in process control, starting with the application of basic statistical process control and leading eventually to automatic process control.¹⁰

2.3

Resolution enhancement techniques

Investigations into imaging led to the discovery by lithographers of earlier work by microscopists on the use of off-axis illumination for enhancing resolution.^11,12,13 Nearly concurrent with interest in off-axis illumination was heightened interest in phase-shifting, a technique that had been introduced earlier.¹⁴ The increase in the amount of activity in resolution enhancement R&D is illustrated in Fig. 2. Only one or two papers on RETs appeared at the SPIE Advanced Lithography Symposium in 1989 and 1990, but this number quickly increased to over 20 papers by 1992. The graph in Fig. 2 exemplifies how a good idea becomes recognized and leads to widespread activity on the method. Investigations into RETs relied heavily on simulation, illustrating how one set of improvements in lithography was based on earlier advances.

There were additional consequences to theoretical explorations of RETs. The simulations showed what types of exposure conditions were required for good resolution and depth-of-focus, and these provided guidance to the makers of exposure tools on what hardware enhancements were needed. For example, earlier models of wafer steppers had fixed numerical aperture and conventional illumination with fixed partial coherence. This gave way to wafer steppers that had variable numerical apertures and variable partial coherence. Later, exposure tools with annular and other forms of offaxis illumination became available.¹⁵

2.4

Optical proximity corrections

As capabilities improved for resolving small features, a new set of phenomena started to be observed. For example, when printing lines with identical mask dimensions, the resulting linewidths were dependent upon whether the line was isolated from other patterns or part of a dense pattern. It was possible to compensate for this effect by adjusting the dimension of the features on the mask, depending upon their proximity to other features. This compensation came to be known as optical proximity¹⁶ corrections, or OPC.

There were other types of patterns, besides long lines, in which it was found efficacious to modify the pattern on the mask in order to print something on the wafer that more closely approximated the designer’s intent. For example, it was long noted that square patterns on masks printed as circles on wafers, with the high spatial-frequency corners being optically filtered.¹⁷ Others noted that when trying to print rectangles, if the narrow dimension was printed on target, the longer axis would print too short.¹⁸ A way to fix this problem was to lengthen the rectangles on the mask so a pattern with the desired dimensions would be printed on the wafer. Similarly, adding serifs to the corners of squares on the mask would allow for printing less round patterns on the wafer. Although these issues with shortening and corners were not a consequence of proximity of one pattern shape to another, the modifications to the mask to achieve a desired shape on the wafer have still come to be referred to as optical proximity corrections, or OPC. The number of papers on OPC presented at the SPIE Advanced Lithography Symposium is shown in Fig. 5. There was a significant jump in the number of papers between 1993 and 1994, with some fall-off after 1995. With continuing advances, OPC remains a topic of papers presented at the SPIE Advanced Lithography Symposium.

Figure 5.

Number of papers on OPC in the proceedings of the SPIE Advanced Lithography Symposium.

2.5

Lithography-design co-optimization

During the transition between 45-nm and 32-nm logic nodes there was not a concurrent significant increase in the resolution of optical exposure tools. As a consequence, to achieve the desired pitches, patterning was required at values of k1= 0.35 and lower. Even with well-stocked RET and OPC toolboxes, at such values for k₁ it became impossible to pattern logic layouts that were direct shrinks of prior designs or ones with only minor modification. This necessitated substantial changes in design styles, and close interactions and cooperation became required between lithographers and designers. For example, unidirectional lines and spaces are more easily patterned at low values of k₁ than complex 2- dimensional shapes. However, significant layout effort was required to avoid enlarged logic cells with this new design style.¹⁹ Sometimes it was necessary to add levels to the process in order to achieve desired cell sizes, but this would add to overall wafer costs.

The need for greater collaboration between lithographers and designers took another quantum leap with the introduction of multiple patterning.²⁰ In addition to the usual design-rule restrictions based on feature size and shape, specific layouts that could not be composed into two patterning steps became prohibited. Electronic design automation (EDA) tools that traditionally had been solely the province of designers needed inputs from lithographers for applications involving interconnects made with multiple patterning.

Defining new technology nodes has become increasingly complicated. Because of design restrictions, shrinks are no longer proportional to changes in pitches. Rather, the size of actual logic and memory cells needs to be determined, after which routing efficiency needs to be calculated. In combination with estimations of wafer costs, the value proposition of a new technology node, in terms of cost per transistor, can be determined. (Fig. 6)

Figure 6.

Work process flow for deciding on new patterning concepts. The RET used for logic and SRAM cells needs to be the same, so teams working on the two types of cells need to converge to a single RET.