Honeywell's submicron polysilicon gate process

Lap S. Chan; Craig K. Hertog; D. W. Youngner

doi:10.1117/12.48917

1 March 1991 Honeywell's submicron polysilicon gate process

Lap S. Chan, Craig K. Hertog, D. W. Youngner

Proceedings Volume 1392, Advanced Techniques for Integrated Circuit Processing; (1991) https://doi.org/10.1117/12.48917
Event: Processing Integration, 1990, Santa Clara, CA, United States

Abstract

This paper describes a manufacturable submicron CMOS polysilicon gate process. A new hydrogen bromide (HBr) plasma chemistry for etching and contrast enhancement material (CEM) for optical lithography have been applied. The HBr chemistry has achieved a selectivity of better than 30: 1 to gate oxide with a vertical side wall profile and no measurable undercutting even with POC13 doped poiy. Because of the low etch rate of photoresist and the CEM process the size change during etch (pre vs. post ) is estimated to be less than O. 05p. per side. In addition the multilayer contrast enhanced photoresist process has been optimized using statistically designed experiments to achieve maximum critical dimension (CD) control resolution and depth of focus. Electrical line width studies show that the total proximity effect due to lithography and etch is about O. O4t. Statistical process control of O. 8O. i. O. 15p. (3) has been achieved and demonstrated on Honeywell''s O. 8p. Radiation Hardened CMOS technology

Citation Download Citation

Lap S. Chan, Craig K. Hertog, and D. W. Youngner "Honeywell's submicron polysilicon gate process", Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); https://doi.org/10.1117/12.48917

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