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10 August 2023 Design of YOLOv2-tiny accelerator based on PYNQ-Z2 platform
Yixuan Zhao, Baolei Hu, Feiyang Liu, Tanbao Yan, Han Gao
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Proceedings Volume 12748, 5th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2023); 1274836 (2023) https://doi.org/10.1117/12.2689581
Event: 5th International Conference on Information Science, Electrical and Automation Engineering (ISEAE 2023), 2023, Wuhan, China
Abstract
Convolutional neural networks (CNNs) have been widely used in the field of image recognition. To meet the massive computational requirements of CNNs, GPUs or other intelligent computing hardware are typically used for data processing. FPGA supports parallel computing and is characterized by programmability, high performance, low energy consumption, and strong stability. In this paper, we improved and optimized the YOLOv2-Tiny algorithm by combining it with the hardware implementation based on FPGA's hardware structure. We divided the neural network tasks and preprocessed data using the 16-bit fixed-point method to reduce hardware resource consumption. By using the PYNQ-z2 development platform to accelerate the YOLOv2-Tiny CNN, we achieved target object detection and recognition. Compared with CPU (i7-10710U), the processing capacity was 2.94 times that of CPU, and the power consumption was 3.1% of CPU.
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Yixuan Zhao, Baolei Hu, Feiyang Liu, Tanbao Yan, and Han Gao "Design of YOLOv2-tiny accelerator based on PYNQ-Z2 platform", Proc. SPIE 12748, 5th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2023), 1274836 (10 August 2023); https://doi.org/10.1117/12.2689581
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KEYWORDS
Field programmable gate arrays
Digital signal processing
Object detection
Image processing
Algorithm development
Convolution
Convolutional neural networks
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