Convolutional neural networks (CNNs) have been widely used in the field of image recognition. To meet the massive computational requirements of CNNs, GPUs or other intelligent computing hardware are typically used for data processing. FPGA supports parallel computing and is characterized by programmability, high performance, low energy consumption, and strong stability. In this paper, we improved and optimized the YOLOv2-Tiny algorithm by combining it with the hardware implementation based on FPGA's hardware structure. We divided the neural network tasks and preprocessed data using the 16-bit fixed-point method to reduce hardware resource consumption. By using the PYNQ-z2 development platform to accelerate the YOLOv2-Tiny CNN, we achieved target object detection and recognition. Compared with CPU (i7-10710U), the processing capacity was 2.94 times that of CPU, and the power consumption was 3.1% of CPU.
As an important technology and research direction to achieve AI, deep learning has been widely applied in the fields of computer vision, speech recognition, and natural language processing. How to effectively accelerate the computing power of deep learning has always been the focus of scientific research. Among various acceleration technologies, FPGA has the advantages of reconfiguration, high performance, small size, and low latency. As more and more FPGA-based neural network accelerators are developed, we notice there is a lack of a complete and detailed overview. In this paper, we give a comparative study of DNN accelerators on FPGA from the aspects of hardware structures, design ideas and optimization strategies. We further compare the performance of different acceleration technologies in different models and present the prospects of the FPGA accelerators for deep learning.
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