High-speed ADC interface design based on JESD204B protocol

Rui Wang; Jianyu Zhang; Chunhua Jiang; Hui Liu

doi:10.1117/12.3012104

21 December 2023 High-speed ADC interface design based on JESD204B protocol

Rui Wang, Jianyu Zhang, Chunhua Jiang, Hui Liu

Proceedings Volume 12970, Fourth International Conference on Signal Processing and Computer Science (SPCS 2023); 129700V (2023) https://doi.org/10.1117/12.3012104
Event: Fourth International Conference on Signal Processing and Computer Science (SPCS 2023), 2023, Guilin, China

Abstract

The JESD204B protocol serves as a high-speed serial interface protocol for analog-to-digital converters (ADC) and field-programmable gate arrays (FPGA), providing enhanced data throughput compared to traditional LVDS interfaces. This paper presents an overview of the high-speed serial interface technology based on the JESD204B protocol, offering a comprehensive explanation of the data link synchronization mechanism and data mapping process on existing hardware platforms. A meticulously designed code logic system is employed to facilitate the high-speed transmission of ADC sampling data to the FPGA. Ultimately, the functionality of the designed code logic is assessed through functional simulation and board-level verification, yielding results that validate its ability to meet the application requirements for high-speed sampling scenarios.

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Rui Wang, Jianyu Zhang, Chunhua Jiang, and Hui Liu "High-speed ADC interface design based on JESD204B protocol", Proc. SPIE 12970, Fourth International Conference on Signal Processing and Computer Science (SPCS 2023), 129700V (21 December 2023); https://doi.org/10.1117/12.3012104

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