The shrinkage of circuit patterns for improvement of the semiconductor device performance has reduced the tolerances in production. To fit in the tolerances, technologies for improving the uniformity of three-dimensional (3D) shapes of circuit patterns inter- or intra- wafers has been developed. Then, we developed a method for quantifying variations in 3D shapes by critical-dimension scanning electron microscopy (CD-SEM), which can measure widths of circuit patterns with high sensitivity. Since variations in the SEM-image signal are caused by 3D-shape variations, in the method, multiple feature values representing the signal detect shape variations. To compare the effect of the variation in each feature value on the shape variation, the amount of variation in the feature values was normalized by local variations in a reference image. Evaluation on etched wafers showed that several features exhibited independent variation trends that were larger than the local fluctuation. Cross-sectional verification confirmed that one of the feature values correlated with the width at the middle height that cannot be seen in top-view, and variations of 0.24 nm can be detected. It is expected that adjusting processing conditions based on this variation trend will efficiently improve the uniformity of the 3D shape.