The edge roughness of straight lines has received intense focus in the past, whereas the edge roughness of contact holes has been relatively unexplored. Reductions in contact hole roughness can be shown to offer improvements in electrical breakdown voltages, or potentially the opportunity for reduced cellsize. This paper introduces two CD-SEM algorithms for characterizing the amplitude and frequency of contact hole edge roughness. When combined, these two metrics proved capable of detecting differences within four wafer pairs with varying dimension and processing. Increased roughness amplitude was shown to correlate to electrical breakdown failures.
While overlay precision has received much focus in the past, overlay accuracy has become more significant with shrinking process budgets. One component of accuracy is the difference between pre-etch (DI) and post-etch (FI) overlay, which is a function of wafer processing parameters. We investigated a specific case of overlay between metal and contact layers of a 0.16 mm SRAM process. This layer was chosen because a significant amount of wafer contraction was observed between DI and FI, resulting in as much as 30nm of DI-FI overlay difference. The purpose of the study was to characterize the systematic DI-FI differences and gain understanding of the wafer processing parameters that affect the DI-FI differences. A designed experiment showed how certain overlay mark widths were less sensitive to processing parameters. AFM profiles of the prior-level overlay marks identified issues with mark widths 1.0um or smaller. By performing localized etches on the inner vs. outer marks of the overlay targets, it was noted that the majority of the wafer contraction was induced by etching the outer (prior level) mark. Production measurements at photo and etch showed the wafer contraction to be fairly stable over a month timeframe and independent of device and exposure tool, though large fluctuation shifts in wafer contraction were noted over a nine-month period. The methods used in this study can be helpful in understanding other DI-FI processing issues.
KEYWORDS: Photoresist materials, Scanning electron microscopy, Monte Carlo methods, Electron beams, FT-IR spectroscopy, Systems modeling, Optical lithography, 193nm lithography, Amplifiers, Scanning probe microscopy
As photolithography platforms move from 248nm to 193nm resist systems, the industry's established dimension measurement technique (CD-SEM) causes significant shrinkage of the resist structures during measurement. Many studies have been done to characterize this effect and look for the factors that influence / reduce this shrinkage. While numerous anecdotal mechanisms have been proposed to explain the shrinkage, few theoretical / empirical equations have been proposed to connect the observed effects to fundamental mechanisms. Models are proposed relating physical properties (accelerating voltage, photoresist density, resist e-beam film shrinkage) to the commonly observed CD 'hammer test' shrinkage profiles. The validity of the model assumptions is tested via Monte Carlo simulations, FTIR, e-beam curing, SPM and ellipsometry. These models explain the shape of the CD response to repeated measurements (exponential decay curve) and the magnitude of the shrinkage. These models also offer insight into why lower accelerating voltages cause reduced CD shrinkage, although the models predict that accelerating voltage should be a much more dominant parameter for CD shrinkage than literature has shown to date. Mass loss and density changes were also characterized during e-beam cure to check the validity of the model assumptions.
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