Dr. Cuiping Zhang Profile

Dr. Cuiping Zhang

at ASML

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Author

Publications (4)

Proceedings Article | 28 April 2023 Presentation + Paper

Physical dose modeling and throughput optimization in EUV computational lithography

Austin Peng, Christopher Kaplan, Jeff Lu, Michael Crouse, Zuanyi Li, Xiaobo Xie, David Rio, Achim Woessner, Alexander Tan, Cuiping Zhang, Xiaoyang Li, Dezheng Sun, Stephen Hsu, Rafael Howell, Joerg Zimmermann

Proceedings Volume 12494, 124940C (2023) https://doi.org/10.1117/12.2657454

KEYWORDS: Source mask optimization, Computational lithography, Nanoimprint lithography, Extreme ultraviolet, Semiconducting wafers, Scanners, Modeling, Reticles, Artificial intelligence, Light sources and illumination

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Proceedings Article | 28 April 2023 Presentation + Paper

A holistic approach to model-based stochastic-aware computational lithography

ChangAn Wang, Yongfa Fan, Mu Feng, Qian Xie, Jazer Wang, Chris Kaplan, Michael Crouse, Xiaoyang Li, Stephen Hsu, Peigen Cao, Yi-Hsing Peng, Stephen Chang, Jun Ye, Youping Zhang, Bin Cheng, Ken Yang, Leiwu Zheng, Jen-Shiang Wang, Austin Peng, Li-Hao Yeh, Cuiping Zhang, Rafael Howell, Alexander Tan, Yiqiong Zhao, Jun Lang, Xiaolong Zhang

Proceedings Volume 12494, 124940B (2023) https://doi.org/10.1117/12.2658508

KEYWORDS: Stochastic processes, Data modeling, Optical proximity correction, Line width roughness, Source mask optimization, Computational lithography, Semiconducting wafers, Modeling, Performance modeling, Photons

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Proceedings Article | 20 March 2018 Presentation + Paper

Freeform mask optimization using advanced image based M3D inverse lithography and 3D-NAND full chip OPC application

Yaobin Feng, Zhiyang Song, Moran Guo, Jun He, Longxia Guo, Gang Xu, Sam Liu, Jingjing Liu, Stephen Hsu, Austin Peng, Andy Yang, Rachit Gupta , Junwei Lu, Victor Peng, Jun Wang, Xiaolong Shi, Leon Liu, Rafael Howell, Cuiping Zhang , Zero Li, Ning-ning Jia

Proceedings Volume 10587, 105870G (2018) https://doi.org/10.1117/12.2297397

KEYWORDS: Photomasks, Source mask optimization, Optical proximity correction, Lithography, SRAF, Semiconducting wafers, Printing, Electroluminescence, Scanning electron microscopy, Pattern recognition

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Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.

The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.

Proceedings Article | 16 October 2017 Presentation + Paper

Machine learning assisted SRAF placement for full chip

Shibing Wang, Jing Su, Quan Zhang, Weichun Fong, Dezheng Sun, Stanislas Baron, Cuiping Zhang, Chenxi Lin, Been-Der Chen, Rafael Howell, Stephen Hsu, Larry Luo, Yi Zou, Yen-Wen Lu, Yu Cao

Proceedings Volume 10451, 104510D (2017) https://doi.org/10.1117/12.2283493

KEYWORDS: SRAF, Machine learning, Lithography, Photomasks, Optical proximity correction, Model-based design, Computational lithography, Data modeling, Image processing

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