The datapath throughput of electron beam lithography systems can be improved by applying lossless image compression to the layout images and using an electron beam writer that contains a decoding circuit packed in single silicon to decode the compressed image on-the-fly. In our past research, we had introduced Corner2, a lossless layout image compression algorithm that achieved significantly better performance in compression ratio, encoding/decoding speed, and decoder memory requirement than Block C4. However, it assumed a somewhat different writing strategy from those currently suggested by multiple electron beam (MEB) system designers. The Corner2 algorithm is modified so that it can support the writing strategy of an MEB system.
The data delivery throughput of electron beam lithography systems can be improved by applying lossless image compression
to the layout image and using an electron beam writer that can decode the compressed image on-the-fly. In earlier
research we introduced the lossless layout image compression algorithm Corner2, which assumes a somewhat idealized
writing strategy, namely row-by-row with a raster order. The MAPPER system has electron beam writers positioned in a
lattice formation and each electron beam writer writes a designated block in a zig-zag order. We introduce Corner2-MEB,
which redesigns Corner2 for MAPPER systems.
The Corner2 algorithm was designed to resolve the data delivery problem on maskless lithography systems.
The Corner2 algorithm utilizes dictionary-based compression to handle repeated circuit components and applies
a transform which is specifically tailored for layout images to deal with irregular circuit components. It obtains
high compression ratios and fast encoding/decoding times while requiring limited decoder memory in the decoder
hardware. Moreover, the entire decompression is simple so that it could be implemented as a hardware add-on
to the lithography writer. However, there is some room for improvement in how we build the dictionary to
handle frequent circuit patterns. In this paper, we introduce an improved way to discover frequent patterns from
the circuit layout images based on binary integer programming. By applying this improved frequent pattern
dictionary, we were able to obtain 4.5-35.8% more compression while maintaining the same Corner2 decoder.
Moreover, this binary integer programming framework could be applied to other binary image compression
problems with similar pattern restrictions.
The data delivery throughput of maskless lithography systems can be improved by applying a lossless image
compression algorithm to the layout images and using a lithography writer that contains a decoding circuit
packed in single silicon to decode the compressed image on-the-fly.
In our past research we have introduced Corner2, a layout image compression algorithm which achieved
significantly better performance in all aspects (compression ratio, encoding/decoding speed, decoder memory
requirement) than Block C4. In this paper, we present the synthesis results of the Corner2 decoder for FPGA
implementation.
The recent algorithm Corner is a transform-based technique to represent a circuit layout image for maskless direct write lithography systems. We improve the lossless circuit layout compression algorithm Corner so that 1. it requires fewer symbols during the corner transform, 2. it has a simpler and faster decoding process, while 3. it requires a similar amount of memory for the decoding process.
The recent algorithm Corner is a transform-based technique to represent a circuit layout image for electron beam direct
write lithography systems. We improve the lossless circuit layout compression algorithm Corner so that 1) it requires fewer
symbols during the corner transform, 2) it has a simpler and faster decoding process, and 3) it requires a similar amount of
memory for the decoding process.
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