A physics-based analytical model is important to understand the working mechanism through process parameters of any innovative material heterostructure. We present an analytical model to calculate the power conversion efficiency of solar cells based on graphene and III-V direct bandgap semiconductors. The model is comprehensively developed by incorporating several current densities obtained from both the generation and recombination processes. Moreover, to obtain a highly efficient Schottky junction solar cell, we propose an optimized structure of graphene/GaAs with lattice-matched passivation and carrier selective layers. The structure has the advantage of surface passivation and photon recycling that reduces interface recombination and ensures more electron–hole pair generation, respectively. It exhibits a theoretical efficiency of >18 % from the analytical model simulation which is later verified by numerical simulation using SCAPS 1D software. The analytical model will provide not only a better understanding of the solar cells’ operation but also a comparative study among them to achieve better efficiency in the future. In addition, the enhanced efficiency of the proposed structure will encourage further research in this field of study.
Device size has now reached the nanoscale range due to advancements in technology and scaling in the fields of very large-scale integration. The single-electron transistor (SET) is a promising solid-state device that can provide an extension for Moore’s law and is suitable for next-generation nanoelectronics design and application. Due to the Coulomb oscillation properties of the SET in addition to the high gain and ultra-low power consumption of the tunnel field effect transistor (TFET), the implementation of the hybrid SET/TFET will primarily benefit high density (nanoscale), low-power integrated circuits (ICs), and fast switching devices. In this study, we present a hybrid model of a graphene-based single electron transistor [1] with an n-type double-gate graphene nanoribbon TFET structure [2] utilized as an integrator. For simplicity, the TFET is used in the shorted gate configuration by connecting both the front and back gates. Following this, we design a fourth order analog low pass filter using the integrator circuit of SET/TFET. With the implementation in SPICE and Matlab, we analyze the transfer function of our proposed filter from its frequency characteristics (Bode plot). Our findings reveal significant roll-off and, as a consequence, increased filtering functions with low power consumption. This study adds to the realization and implementation of SET/TFET into applications where high frequency contributes to the reliability, performance, and low power required for nanoscale devices and designs.
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