As a tremendous amount of data is being created exponentially day by day, integrated optical computing starts to attract lots of attention recently due to the bottleneck in the continuation of Moore’s law. With the rapid development of micro/nano-scale optical devices, integrated photonics has shown its potential to satisfy the demand of computation with an ultracompact size, ultrafast speed, and ultralow power consumption. As one of the paradigms in optical computing, the electro-optic logic that combines the merits of photonics and electronics has made considerable progress in various fundamental logic gates. It therefore becomes very critical to develop an automated design method to synthesize these logic devices for large-scale optical computing circuits. In this paper, we propose a new automated logic synthesis algorithm based on And-Inverter Graphs (AIGs) for electro-optic computing. A comprehensive component library of electro-optic logic is summarized with several new proposed logic gates. As an example, a large-scale ripple-carry full adder which serves as the core part of the arithmetic logical unit (ALU) is presented. In the design, all the electrical signals could be applied simultaneously at every clock cycle and then the light could process the signals through every bit at the speed of light without any delay accumulated. High-speed experiment demonstrations are carried out, which show its potential in future high-speed and low-power-consumption optical computing.
Due to ever increasing demand for information bandwidth, and with electronics approaching their performance limit, there has been a renewed interest in using optical logic for computing and signal processing over the past decade. System advantages that the optical schemes promise over the conventional electrical schemes including but not limited to: significant reduction of gate latency, ultra-low energy consumption, and simplified layout architecture. For example, adding is the fundamental operation for computation. However, though it has a concise layout, a conventional electrical carry-ripple adder will be too slow for many-bit addition due to excessive carry propagation delay. Thus, modern microprocessors all have to use much more complicated structures such as parallel prefix adders to obtain satisfactory performance while they come with inevitable power penalty. The greater the number of bits, the more complex and power hungry the adder will become. In this paper, we propose a silicon photonics based architecture of carry-ripple adder, which utilizes the particular merit of light that interference, for future high-speed and low-power consumption optical computing. In our proposed carry-ripple adder, the critical path will be built with optical switch and optical signals will be modulated to carry information. As all of the optical switches could operate simultaneously, the unpleasant accumulated gate latency from the electrical approach will be removed. Silicon photonic based optical switches are promising candidates to implement the adder due to their compact sizes, which could significantly reduce the capacitances and energy-consumption.
Due to the bottleneck in the continuation of Moore’s law as well as the drastically increasing trend of bandwidth, silicon photonics has emerged as the most promising candidate for implementing next-generation communication networks with ultralow power and ultrahigh speed. Recently, optical computing in integrated photonics, which outperforms electrical counterparts both in power consumption and bandwidth, has attracted a renewed interest due to the accessibility and maturity of ultracompact passive and active integrated components. However, up to now, most of relevant research about optical computing still focus on the realization of fundamental logic gates, not even close to feasible large-scale computing system. In this paper, we demonstrate a high-speed ripple-carry electro-optic full adder using micro-resonators. This approach adopts photons instead of electrons to realize logic operations as well as transfer carry signals from one bit to the next, while all the control signals of operands are applied simultaneously at and within every clock cycle. Thus, the severe latency issue that accumulates as the size of full adder increases can be circumvented, allowing for the improvement in computing speed. This approach also outperforms the conventional electrical counterpart in terms of power consumption due to the relatively smaller propagation loss and switching energy.
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