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Yuan Guan

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Proceedings Article | 7 May 2024 Paper

A fast hardware implementation method of interrupt handling based on Armv8-M architecture

Jun Ma, Hao Zhao, Xige Zhang, Liang Liu, Yuan Guan, Chenxi Wang

Proceedings Volume 13161, 131610H (2024) https://doi.org/10.1117/12.3025851

KEYWORDS: Information security, Clocks, Lawrencium, Data storage, Logic, Parallel computing, Computer hardware, Switches, Reflection, Operating systems

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The interrupt response speed can reflect the CPU's processing speed for external events, and is a very important indicator for measuring CPU performance. In the field of real-time applications, interrupt response speed is an important manifestation of real-time performance and an important aspect of optimizing CPU implementation. When responding to interrupts, especially in CPU implementations that allow interrupt nesting, it usually involves saving the interrupt context. Only after saving the interrupt context can the CPU execute instructions related to interrupts in the interrupt handling function. This paper presents a hardware implementation scheme for backup registers. One application method is to quickly save interrupt context information to the backup registers when responding to an interrupt, and then save the contents of the backup registers to the stack parallel in the background when executing interrupt processing function instructions to improve interrupt response speed. Another application method is to restore the interrupt context from the backup register directly, or to obtain the current interrupt context information from the current interrupt stack position in the background in parallel during the execution of the interrupt processing function instruction to the backup registers. When the current interrupt returns, the interrupt context can be directly restored from the backup registers to improve the speed of interrupt return. Hardware stack identification can be used to indicate whether interrupt nesting can be performed or not. Whether interrupt context can be restored from the backup registers or not can be checked by the effective hardware identification for backup registers information. The process of parallel reading interrupt contexts from stack to backup registers in the background can be controlled by recording the stack position corresponding to each interrupt context in hardware.

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