Mr. ZeXi Deng Profile

ZeXi Deng

at Semiconductor Manufacturing International Corp

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Author

Publications (10)

Proceedings Article | 23 March 2020 Paper

Fast OPC repair flow based on machine learning

Bailing Shi, Rock Deng, Zhongli Shu, Yu Zhu, Yuanying Tu, Sun Chen

Proceedings Volume 11328, 113281B (2020) https://doi.org/10.1117/12.2552731

KEYWORDS: Optical proximity correction, Machine learning, Data modeling, Metals, Semiconductor manufacturing, Semiconductors, SRAF, General applications engineering

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Proceedings Article | 26 September 2019 Paper

Investigation of reducing mask writing time with shot count management solution

Linna Cong, Shizhi Lyu, Mingjing Tian, Feng Liu, Min Zhang, Zexi Deng, Chunli Zhang, Ming Chen

Proceedings Volume 11148, 1114810 (2019) https://doi.org/10.1117/12.2529862

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Critical dimension metrology, Data modeling, Optical alignment, Data analysis, Mask making, Error analysis, Tolerancing

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Proceedings Article | 20 March 2018 Paper

A novel method to fast fix the post OPC weak-points through Calibre eqDRC application

YaDong Jin, Shizhi Lyu, ZeXi Deng, Cong Lu

Proceedings Volume 10587, 1058715 (2018) https://doi.org/10.1117/12.2292695

KEYWORDS: Optical proximity correction, Design for manufacturing, Semiconducting wafers, Computer programming, Error analysis, Photomasks, Graphic design, Human-machine interfaces, Resolution enhancement technologies, Optics manufacturing

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Proceedings Article | 18 March 2015 Paper

Automation for pattern library creation and in-design optimization

Rock Deng, Elain Zou, Sid Hong, Jinyan Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding, Jason Huang

Proceedings Volume 9427, 94270R (2015) https://doi.org/10.1117/12.2087100

KEYWORDS: Manufacturing, Metals, Lithography, Optical lithography, Silicon, Failure analysis, Electroluminescence, Semiconductor manufacturing, Image classification, Library classification systems

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Semiconductor manufacturing technologies are becoming increasingly complex with every passing node. Newer technology nodes are pushing the limits of optical lithography and requiring multiple exposures with exotic material stacks for each critical layer. All of this added complexity usually amounts to further restrictions in what can be designed. Furthermore, the designs must be checked against all these restrictions in verification and sign-off stages. Design rules are intended to capture all the manufacturing limitations such that yield can be maximized for any given design adhering to all the rules. Most manufacturing steps employ some sort of model based simulation which characterizes the behavior of each step. The lithography models play a very big part of the overall yield and design restrictions in patterning. However, lithography models are not practical to run during design creation due to their slow and prohibitive run times. Furthermore, the models are not usually given to foundry customers because of the confidential and sensitive nature of every foundry's processes. The design layout locations where a model flags unacceptable simulated results can be used to define pattern rules which can be shared with customers. With advanced technology nodes we see a large growth of pattern based rules. This is due to the fact that pattern matching is very fast and the rules themselves can be very complex to describe in a standard DRC language. Therefore, the patterns are left as either pattern layout clips or abstracted into pattern-like syntax which a pattern matcher can use directly. The patterns themselves can be multi-layered with "fuzzy" designations such that groups of similar patterns can be found using one description. The pattern matcher is often integrated with a DRC tool such that verification and signoff can be done in one step. The patterns can be layout constructs that are "forbidden", "waived", or simply low-yielding in nature. The patterns can also contain remedies built in so that fixing happens either automatically or in a guided manner. Building a comprehensive library of patterns is a very difficult task especially when a new technology node is being developed or the process keeps changing. The main dilemma is not having enough representative layouts to use for model simulation where pattern locations can be marked and extracted. This paper will present an automatic pattern library creation flow by using a few known yield detractor patterns to systematically expand the pattern library and generate optimized patterns. We will also look at the specific fixing hints in terms of edge movements, additive, or subtractive changes needed during optimization. Optimization will be shown for both the digital physical implementation and custom design methods.

Proceedings Article | 18 March 2015 Paper

An efficient lithographic hotspot severity analysis methodology using Calibre PATTERN MATCHING and DRC application

ZeXi Deng, ChunShan Du, Lin Hong, LiGuo Zhang, JinYan Wang

Proceedings Volume 9427, 94270Y (2015) https://doi.org/10.1117/12.2086041

KEYWORDS: Metals, Manufacturing, Lithography, Design for manufacturing, Optical proximity correction, Bridges, Databases, Visualization, Phase modulation, Electronic design automation

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Proceedings Article | 20 October 2006 Paper

An effective layout optimization method via LFD concept

Ching-Heng Wang, Zexi Deng, Gensheng Gao, Chi-Yuan Hung

Proceedings Volume 6349, 63492Z (2006) https://doi.org/10.1117/12.685727

KEYWORDS: Manufacturing, Data modeling, Process modeling, Optical proximity correction, Design for manufacturability, Calibration, Semiconducting wafers, Metals, Image processing, Scanning electron microscopy

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Proceedings Article | 20 May 2006 Paper

Model based SRAF insertion check with OPC verify tools

Chi-Yuan Hung, Zexi Deng, Gensheng Gao, Liguo Zhang, Qingwei Liu

Proceedings Volume 6283, 628332 (2006) https://doi.org/10.1117/12.681820

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Lithography, Semiconducting wafers, Printing, Data modeling, Process modeling, Manufacturing, Optical lithography

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Proceedings Article | 20 March 2006 Paper

A methodology to take LER effect into OPC modeling algorithm

Chi-Yuan Hung, Qingwei Liu, Zexi Deng, Liguo Zhang

Proceedings Volume 6154, 615439 (2006) https://doi.org/10.1117/12.651552

KEYWORDS: Line edge roughness, Data modeling, Optical proximity correction, Process modeling, Semiconducting wafers, Data processing, Physics, Optical lithography, Photomasks, Model-based design

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Proceedings Article | 5 May 2005 Paper

Line end design intent estimation using curves

Chi-Yuan Hung, Gensheng Gao, Steven Zhang, Ze-Xi Deng, Christopher Cork, Lawrence Melvin, Yan Jiang

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.604526

KEYWORDS: Optical proximity correction, Silicon, Lithography, Design for manufacturing, Semiconductors, Photomasks, Logic, Lithographic illumination, Manufacturing, Transistors

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Semiconductor foundries need to have a single, standard mask preparation procedure to deal with the large number of designs they receive. This data is typically of two sorts; the random logic over which they have little control of how the design intent is represented; and cells from dense arrays such as memory, often with design rule violations, whose OPC correction needs to be precisely optimized to achieve best yield and device performance. Occasionally the input data will contain sub-resolvable notches and extensions, which while not violating DRC specifications, would, if filled, result in DRC violations. This may be due to a non DFM aware automated layout tool, or a designer aggressively trying to minimize circuit density. In practice it is worthwhile to clean up these notches to ease OPC correction. Doing this should not result in printability errors as these notches typically represent a more complex curved design intent that cannot be accurately represented due to the restrictions imposed by the limited number of polygon edge directions available for layout. Similarly, memory cell layouts often have significant implied curvature. These may only be corrected properly if the OPC target point is defined precisely for each individual segment. In general, letting the OPC correction engine correct a layout defined by a realistic, curved target shape gives better quality corrections with greater process window. The challenge for the OPC engineer working in a foundry is therefore to determine a clean-up methodology for incoming data and to correctly apply the design intent, where necessary, from the original pre-cleanup data. A programmable OPC engine gives the user flexibility in optimizing the set of rules embedded in the OPC cleanup and correction recipes. These embed within them the algorithms to interpret the rounding on the desired silicon image not only for line-ends and corners of random logic but also the more complex curved silicon images and tolerances required by memory cells.

Proceedings Article | 27 January 2005 Paper

Increasing post OPC layout verification coverage using a full-chip simulation based verification method

Chi-Yuan Hung, Yong Dong Wang, Ze Xi Deng, Gen Sheng Gao, Ming Hui Fan

Proceedings Volume 5645, (2005) https://doi.org/10.1117/12.572711

KEYWORDS: Optical proximity correction, Resolution enhancement technologies, Photomasks, Semiconducting wafers, Process modeling, Lithography, Bridges, Reticles, Design for manufacturing, Silicon

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Showing 5 of 10 publications

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