Lithographic chip identification: meeting the failure analysis challenge

Lynn Perkins; Kevin G. Riddell; Warren W. Flack

doi:10.1117/12.59819

1 June 1992 Lithographic chip identification: meeting the failure analysis challenge

Lynn Perkins, Kevin G. Riddell, Warren W. Flack

Proceedings Volume 1673, Integrated Circuit Metrology, Inspection, and Process Control VI; (1992) https://doi.org/10.1117/12.59819
Event: Microlithography '92, 1992, San Jose, CA, United States

Abstract

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

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Lynn Perkins, Kevin G. Riddell, and Warren W. Flack "Lithographic chip identification: meeting the failure analysis challenge", Proc. SPIE 1673, Integrated Circuit Metrology, Inspection, and Process Control VI, (1 June 1992); https://doi.org/10.1117/12.59819

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KEYWORDS

Reticles

Semiconducting wafers

Manufacturing

Process control

Integrated circuits

Optical alignment

Inspection

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