In this work, we demonstrate a self-aligned litho-etch litho-etch (SALELE) process flow for 18nm pitch patterning of subtractive Ru structures. This process combines many individual steps from a standard damascene double patterning flow with a spacer pull process to adapt it for subtractive patterning. Requiring two EUV exposures, this process flow enables a broad design space comparable to existing SALELE solutions for damascene integrations. Utilizing this process flow, we have demonstrated successful patterning of complex designs including intertwined comb-serpentines and various mixed pitch patterns. We report matched resistance for both mandrel and non-mandrel resistors. Additionally, we demonstrate equivalent yields for 1mm long intertwined comb-serpentine structures with serpentines formed from both mandrel and non-mandrel patterns.
Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.
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