Vertical field effect light emitting transistors (VFELETs) have an advantage over lateral ones because they have the ability to conveniently decrease the channel volume. In the VFELET both current density and cut-off frequency are enhanced by this. Current work presents a highly efficient VFELET simulation process based on CdSe quantum dots in which the ITO gate is accompanied by dielectric Al2O3. While using AgNW as drain material and Au as source. By changing gate voltage as well as Vds, the output of the VFELET is greatly improved. The 10-5A Id has been achieved by using Vgs 0.4, 0.8, 1.2 and 1.6V. In addition, a higher EQE (2.6 %) and maximum luminance (1.1 × 104 cd m-2) have also been achieved in current work.
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