Mr. Takayuki Morisawa Profile

Takayuki Morisawa

at Lasertec Corp

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Proceedings Article | 21 November 2023 Presentation + Paper

Realizing EUV photomask defectivity qualification by actinic mask review system

Jiun-Lung Lu, Chien-Hsing Lu, Hsin-Fu Tseng, Vincent C. Wen, Chun-Hung Chen, Yi-An Huang, Yung-Sheng Chang, Sagar Trivedi, Danping Peng, Takayuki Morisawa, Hiroki Miyai

Proceedings Volume 12751, 127510P (2023) https://doi.org/10.1117/12.2688176

KEYWORDS: Extreme ultraviolet, Photomasks, Reticles, Printing, Semiconductors, Semiconducting wafers, Integrated circuits, Source mask optimization, Risk assessment, Reliability

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The EUV reticle masking process has enabled the creation of smaller and more intricate integrated circuits, which are essential components of modern electronic devices. However, ensuring defect-free control and evaluation in the cutting-edge EUV reticle masking process is a challenging task. Currently, every potential defect must be judged by wafer printing assessment for almost 3 days, which can be both time-consuming and expensive, and even commercial approaches are incapable of meeting the demands of high-volume manufacturing. In this paper, we successfully developed the EUV Actinic Mask Review System (AMRS) to emulate wafer printability behaviors, utilizing a stable LPP EUV source with over 95% available time and a specialized TSMC-made SMO to achieve high throughput for more than 80 sites/hr. In addition, various EUV resist models have been developed to emulate the risk defect printing assessment with good matching results, and an in-house automation EUV defect analysis platform was developed to achieve fast and accurate areal image measurement. With this solution, all EUV repaired and potential defects, including 18nm HP L/S, ML defects, and even through EUV pellicle defects, can be addressed in technology nodes N5, N3, and beyond N3, on the brand-new actinic review platform. The development of the EUV Actinic Mask Review System represents a significant advancement in ensuring the quality and reliability of semiconductor devices. It provides a practical solution to the challenges posed by the EUV reticle masking process and enables the production of defect-free integrated circuits, paving the way for the continued innovation and progress of the semiconductor industry.

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