Proceedings Article | 28 March 2017
Gian Francesco Lorusso, Takeyoshi Ohashi, Astuko Yamaguchi, Osamu Inoue, Takumichi Sutani, Naoto Horiguchi, Jürgen Bömmels, Christopher Wilson, Basoene Briggs, Chi Lim Tan, Tom Raymaekers, Romain Delhougne, Geert Van den Bosch, Luca Di Piazza, Gouri Sankar Kar, Arnaud Furnémont, Andrea Fantini, Gabriele Luca Donadio, Laurent Souriau, Davide Crotti, Farrukh Yasin, Raf Appeltans, Siddharth Rao, Danilo De Simone, Paulina Rincon Delgadillo, Philippe Leray, Anne-Laure Charley, Daisy Zhou, Anabela Veloso, Nadine Collaert, Kazuhisa Hasumi, Shunsuke Koshihara, Masami Ikota, Yutaka Okagawa, Toru Ishimoto
KEYWORDS: Metrology, Critical dimension metrology, Scanning electron microscopy, 3D metrology, Back end of line, Logic, Standards development, Germanium, Algorithm development, Process control, Resistance, Overlay metrology, Oxides, Etching, Statistical analysis
The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.
