The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.
Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm
technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer
formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of
SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires
precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In
our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the
results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching
performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with
mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We
reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is
capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern
pitch and stack layer thickness on lateral etch results have been studied by simulation.
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