Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process

Martin P. Karnett; Steven G. Qian; Todd Mitchell; Vijaya Subramaniam; Harlan Sur; Bradley J. Haby; Hunter B. Brugge

doi:10.1117/12.395729

18 August 2000 Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process

Martin P. Karnett, Steven G. Qian, Todd Mitchell, Vijaya Subramaniam, Harlan Sur, Bradley J. Haby, Hunter B. Brugge

Proceedings Volume 4181, Challenges in Process Integration and Device Technology; (2000) https://doi.org/10.1117/12.395729
Event: Microelectronic Manufacturing, 2000, Santa Clara, CA, United States

Abstract

Bitmap and electrical microprobe techniques were employed to detect and isolate NMOS gate depletion within the SRAM cells of our 0.20micrometers Complementary Poly CMOS process. This gate depletion problem led to a 3X drop-off in device drive current and about a 300mV increase in threshold voltage. These shifts in device performance produced massive circuit failures within memory circuits and zero yield at wafer probe. Experiments were performed towards conclusively identifying and resolving this gate depletion failure mechanism. Several process modifications were implemented towards eliminating the NMOS gate depletion problem without compromising our margin against PMOS boron penetration. These process improvements led to dramatic increases in probe yield.

Citation Download Citation

Martin P. Karnett, Steven G. Qian, Todd Mitchell, Vijaya Subramaniam, Harlan Sur, Bradley J. Haby, and Hunter B. Brugge "Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process", Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); https://doi.org/10.1117/12.395729

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