In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.
Extreme Ultraviolet lithography with a numerical aperture of 0.55 will bring an improved optical contrast for contact hole layers and via layers. This improved optical contrast should lead to a reduction in the number of stochastic defects for these layers. To quantify this reduction, an adequate inspection methodology is required that can detect, in addition to the standard missing and merging defects, contact holes that are only partially opened. In this work we demonstrate a technique that uses backscattered electrons to detect these defects. In the first phase the beam-settings in a top-down scanning electron microscope are optimized to visualize holes that have been confirmed to be partially opened contact holes by either voltage contrast or transmission electron microscope. In the second phase these beam conditions are implemented on a massive metrology e-beam tool that has an increased throughput and therefore can collect information on millions of contact holes. In the last phase we show how this inspection can be used to enlarge the failure free latitude on a 36nm hexagonal contact hole pattern and to optimize the litho and etch conditions to minimize the number of stochastic defects on product wafers.
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