Edge placement error (EPE) has become a critical metric for ensuring patterning accuracy and optimizing the process window in semiconductor manufacturing. Initially introduced to measure optical proximity correction (OPC) errors, EPE now encompasses a broader set of parameters, including overlay (OV), critical dimension uniformity (CDU), and line width roughness (LWR), making it essential for managing the complexity of advanced multi-patterning processes. Despite its importance, directly measuring EPE remains challenging due to the intricate nature of modern semiconductor devices, often requiring statistical methods for estimation. This paper demonstrates the use of secondary electron (SE) and backscattered electron (BSE) imaging to improve the accuracy and practicality of EPE measurement. By optimizing BSE imaging conditions, layers such as contact and can be visualized simultaneously, allowing for more direct calculations of OV and EPEinterlayer. The optimized imaging conditions also enhance edge definition, improving pattern accuracy and process control. Our results show that SE and BSE imaging offer a more precise method for evaluating EPE and contribute to a better understanding of the factors influencing process window control.
OPC technology is one of the most key procedures in IC manufacturing. When it came to the 90nm node process, lithography table-driven OPC technology was replaced gradually by the model-based OPC. In the early stage, optical model played a dominant role in whole OPC model, resist model provided limited adjustment on aerial images. As the technical node continue shrinking, and pattern complexity increasing, simplified resist model can’t perform resist behavior sufficiently. The properties of strong shrinkage and queue-time sensitivity posed a great challenge to resist modeling. Plenty of new resist model forms are introduced to describe the complex properties. Huge amounts of SEM measurement data are in need to serve model coverage for the complex pattern structures. Currently the gauge amount of measurement data could be over 10 thousands, OPC modeling becomes a big CPU and time consumer. In order to balance the run time and model accuracy, gauges are down sampled with random selection. Usually, around 5000 gauges are used for model calibration, and the left gauges are used for model verification. The weighted RMS values between calibration and verification should be in the same level, which represents the gauge selection could be considered as the reasonable replacement for the whole gauge data base. In this paper, we proposed a SONR (State Of Nature Reduction)- based gauge down sampling method. The SONR is a tool, which could classify the pattern structures and measurement values into specific clusters. With its help, the gauge amount for model calibration could be shrunk from 5000 to 3000. This method accelerated model calibration speed by nearly 1x time. In the meanwhile, it decreased CPU and license consume, and shorten R&D cycle of new OPC models.
Transmission Electron Microscopy (TEM) uncertainty can stem from sample preparation, TEM measurement, and sample tilt during imaging, leading to result variations. Since TEM data serves as a reference for optical critical dimension (OCD) setup, reducing TEM uncertainty is essential to enhance OCD measurement accuracy. This work aims to address these challenges by optimizing sample preparation techniques, refining TEM measurement protocols, and minimizing sample tilt effects. By systematically identifying and mitigating sources of uncertainty, we aim to establish more reliable TEM data. The improved accuracy of TEM measurements will, in turn, enhance the precision of OCD setups, leading to more consistent and accurate process control in semiconductor manufacturing. This initiative not only aims to bolster TEM reliability but also to ensure the robustness of OCD measurements, thereby improving overall process quality and yield.
KEYWORDS: Etching, System on a chip, Image processing, Sensors, Lithography, Semiconducting wafers, Distance measurement, Process control, Transistors, Signal to noise ratio
BackgroundThe self-aligned double-patterning (SADP) process is being used extensively to overcome the lithographic resolution limit in the manufacture of integrated circuits. One use case is fin definition in a fin field-effect transistor. Fin cut layers are applied to modify the fins to the requirements of the device designs.AimThe traditional secondary electron (SE) imaging exhibits a disadvantage in the process controlling the fin cut layers, and fin damage defects were observed. This work aims to improve the monitoring and controlling capabilities for the process quality of fin cut layers.ApproachA specially designed fin cut process flow and a backscattered electron (BSE) imaging technique are applied to check the process quality. The patterns formed through the fin cut etch and the fin structures are identified and measured simultaneously in one BSE image.ResultsBy measuring the edge-to-edge distance, pitch walking (PW) of fins, and overlay (OV), the root cause of the fin damage is revealed. The linear fitting model and third-order fitting model are applied to reduce the edge placement error (EPE). The edge distance protecting the “at risk” fin is enlarged from 5.6 to 11.6 nm. The range of the distance is reduced from 11.6 to 8.1 nm, and the improvement in standard deviation is about 33%.ConclusionsThis work shows the capability of the BSE imaging technique in the characterization of fin cut layers and the potential in process window improvement restricted to fin damage defects.
Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.
This Conference Presentation, “A holistic study of edge placement error on fin cut layer in self-aligned double patterning process,” was recorded at SPIE Photonics West held in San Francisco, California, United States.
As technology progress with scaling to meet the market requirements, the patterning characterization of dense features suffers a significant challenge for current optic tools, and measurement accuracy will be an important index and great challenge as well. Patterning can mostly be characterized with index of overlay (OVL) and CDU (critical dimension uniformity) measurement. When you break down the budget of the overlay error, one of the challenges is a gap of measurement results between scribe and device, where provides improper information to be used in overlay correction and causes process anomaly (excursion) detection, resulting in a low yield at the end of the production process. An eBeam tool, using high electron landing energies while utilizing the ElluminatorTM technology[1] for improvement backscattered electrons (BSE) imaging efficiency, can be utilized to directly capture OVL performance of device unit in-die, including local and global level, due to BSE function of eBeam tool[2]. In this paper, we demonstrate overlay measurement of M0 to Poly line in device for advanced logic node (only OVL X measurement), obtaining Overlay gap between in-die and scribe line to capture the actual behavior of device unit in-die. Massive OVL data is measured using eBeam tool with fast speed and high resolution, and local OVL results have been analyzed in detail. We’ve quantified what is the impact of overlay correction by different measurement ways whether it depends on optical tool or eBeam tool and benefits yield improvement.
Photoresist (PR) profile and defect are very important in semiconductor manufacturing, the abnormal PR profile and defect will cause the following process abnormal even affect the device performance. For example, under-cut PR profile is easy to pattern collapse, while footing will cause the pattern bottom bridge, both of these will cause device hard fail. PR profile is affected by lots of factors, such as bottom reflectivity, PR properties, focus, etc. But an important impacted factor is often ignored, that is the film property contacting PR. If the property of under film does not match with PR, it will affect PR profile seriously, even bring defect issue. So investigating the friendly interface is a meaningful topic. In this paper, we focus on the effect of film treatment on PR profile and defect. Through the experiments, the methods including O2 treatment, heat treatment, and wet treatment, the friendly methods to lithography are chosen, and the possible mechanism is proposed. The film treatment method provides us a new way to improve defect or PR profile, and further improve the lithography process window.
The requirement of overlay performance, which is determined by alignment process during exposure and overlay measurement process, is getting tighter as technology node shrinks in integrated circuit. Mark design has drawn a lot of attention since appropriately designed marks can guarantee process compatibility and sufficient device performance tracking property. Cut layers are widely used in FinFet to define active area formed by SADP (Self-aligned double patterning) or SAQP (Self-aligned quadruple patterning), of which the mark design is especially challenging for diffusion break layer since it is a cut layer that landing on three dimensional fin structure and will be aligned to.
In this paper, mark design of diffusion break layer is investigated, including alignment marks and overlay marks with various substrates and segmentations. It’s recommended that the whole process from mark definition by lithography to final formation of mark after etch should be well taken into consideration during mark design, along with substrate and segmentation to avoid defect and achieve qualified signal as well.
The reduction of line width and edge roughness (LWR & LER) becomes increasingly challenging with development of integrated circuit manufacturing industry, especially with the application of multi-patterning technology. Recent years, unbiased roughness method was well received and applied in LWR & LER characterization by using power spectral density (PSD) analysis. Measurement noise in scanning electron microscope (SEM) can be identified in the high frequency region of PSD curve. By subtracting electron beam noise effect, the unbiased LWR & LER are gotten. In our research, unbiased LWR & LER under different lithography process conditions, including reflectivity of bottom anti-reflection coating (BARC) materials, photo resists (PR), illuminations, post-apply bake (PAB) and post exposure bake (PEB) temperatures, were investigated by PSD analysis. For some of the above conditions, post-develop and post-etch LWR were also studied.
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