Researchers occasionally use a single photomask to create a stacked structure with identical patterns. This method is cost-effective but also challenging for precise overlay control, due to the lack of coupled overlay marks between successive layers. In this paper, an innovative approach has been developed to address this problem. By shifting the exposure field with a specific offset, the outer overlay mark of the previous layer and the inner overlay mark of the current layer are aligned to the same coordinate position, allowing for accurate measurement of the overlay error. The raw overlay measurement values are then modeled using polynomials and compensated during subsequent runs. The effectiveness of this method has been demonstrated with experiment wafers, and PFA (Physical Failure Analysis) result further confirmed its feasibility for achieving precise overlay in such applications.
Line edge roughness (LER) played more critical- role with the semiconductor manufacturing keep shrinking down to new technology nodes. From our previous study, the larger exposure area gives positive impact to LER performance, as more photons can be captured by photoresist, reducing the randomness of photoacid distribution and make line edge smoother. In this paper, we further investigate the litho process impact factors for LER, including Normalized Image Log-Slope (NILS) and exposure energy. Simulation model was setup on top of experiment data, and further expand to different critical dimension (CD) and pitch conditions.
Inverse lithography technology (ILT) is an emerging computational lithography technique that utilizes advanced mathematical algorithms to optimize the mask pattern based on the desired wafer image. Compared with conventional optical proximity correction (OPC), ILT offers advantages in enhancing process window (PW) and reducing edge placement error (EPE) However, the mask writing time and the complexity of the mask writing process is significantly increased due to the complex mask pattern. The current approach involves Manhattanizing curve features to achieve nearly equivalent image quality on a wafer, but the relationship between the Manhattan levels of ILT and improvements in on-wafer performance has not been fully explored. This paper explores the effects of conventional OPC and Manhattanized ILT on on-wafer image fidelity, with a particular focus on the effectiveness of Manhattanized ILT in improving PW and reducing mask writing time. The study compares conventional OPC and Manhattanized ILT to evaluate their lithography performance across specific hotspot patterns. The findings reveal that Manhattanized ILT significantly enhances PW, while also evaluating the trade-offs between mask writing time and PW improvements. Additionally, this study emphasizes the significance of Manhattanized ILT in enhancing EPE.
In recent years, Inverse Lithography Technology (ILT) has been widely used as a new mask correction technology to further improve the imaging performance in advanced imaging at low-k1 lithography regime. Compared to the conventional Optical Proximity Correction (OPC), ILT enables better process window (PW), edge placement error (EPE) specially for 2D pattern, etc. However, ILT naturally generates more complex, nonrectilinear mask shapes, which is a challenge to accurately characterize mask pattern critical dimensions. Accurate characterization of the written ILT Mask is crucial for tuning the ILT Mask manufacturing process, establishing accurate ILT models and quantitatively evaluating the impact of Mask error on wafer imaging performance. Applying contour-based mask quality characterization instead of traditional gauge-based method for non-rectilinear mask dimensions has been considered as a more reliable solution. In this work, we’ve developed an offline batch contour-based methodology flow. It includes contour extraction from SEM images, contour-layout alignment, SEM contours GDS merge, polygon-based SEM contour GDS analysis, statistics and visualization. Based on this methodology flow, we’ve quantified an ILT Mask which has been manufactured by a Variable Single Beam e-Beam writer. Besides, we’ve explored the impact of mask quality on wafer imaging performance based on a clipped mask contour GDS and ILT model. Combined with simulation data on an ideal mask GDS and actual on wafer imaging data we able to separate mask impact on wafer imaging performance from other process fluctuations.
Roughness cannot be ignored as feature sizes shrink with Moore's Law, since it has potential to influence the device's performance. The roughness is usually described by line edge roughness (LER) and line width roughness (LWR). LER is the deviation of a feature edge from its ideal shape and is defined as three times the standard deviation, the deviation from the average line width is defined as LWR. For a certain critical dimension (CD) and pitch, there are many factors that can contribute to the roughness in the lithography process, such as source, mask optimizations, photoresist types and its processing, etc. An in-depth insight of the roughness formation mechanisms is essential to improve LER. This study employs photoresist process simulation to analyze LER, offering an efficient alternative to silicon data collection. Simulation analysis is carried out to examine the key factors influencing LER, including quencher concentration, photoacid diffusion length, PEB temperature. Concurrently, the study also delves into the impact of photoresist resin molecular composition and the development process on roughness. By using simulation to understand and predict roughness, the research provides insights into optimizing lithography parameters, thereby improving process stability and minimizing roughness formation.
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