Inverse lithography technology (ILT) is an emerging computational lithography technique that utilizes advanced mathematical algorithms to optimize the mask pattern based on the desired wafer image. Compared with conventional optical proximity correction (OPC), ILT offers advantages in enhancing process window (PW) and reducing edge placement error (EPE) However, the mask writing time and the complexity of the mask writing process is significantly increased due to the complex mask pattern. The current approach involves Manhattanizing curve features to achieve nearly equivalent image quality on a wafer, but the relationship between the Manhattan levels of ILT and improvements in on-wafer performance has not been fully explored. This paper explores the effects of conventional OPC and Manhattanized ILT on on-wafer image fidelity, with a particular focus on the effectiveness of Manhattanized ILT in improving PW and reducing mask writing time. The study compares conventional OPC and Manhattanized ILT to evaluate their lithography performance across specific hotspot patterns. The findings reveal that Manhattanized ILT significantly enhances PW, while also evaluating the trade-offs between mask writing time and PW improvements. Additionally, this study emphasizes the significance of Manhattanized ILT in enhancing EPE.
In recent years, Inverse Lithography Technology (ILT) has been widely used as a new mask correction technology to further improve the imaging performance in advanced imaging at low-k1 lithography regime. Compared to the conventional Optical Proximity Correction (OPC), ILT enables better process window (PW), edge placement error (EPE) specially for 2D pattern, etc. However, ILT naturally generates more complex, nonrectilinear mask shapes, which is a challenge to accurately characterize mask pattern critical dimensions. Accurate characterization of the written ILT Mask is crucial for tuning the ILT Mask manufacturing process, establishing accurate ILT models and quantitatively evaluating the impact of Mask error on wafer imaging performance. Applying contour-based mask quality characterization instead of traditional gauge-based method for non-rectilinear mask dimensions has been considered as a more reliable solution. In this work, we’ve developed an offline batch contour-based methodology flow. It includes contour extraction from SEM images, contour-layout alignment, SEM contours GDS merge, polygon-based SEM contour GDS analysis, statistics and visualization. Based on this methodology flow, we’ve quantified an ILT Mask which has been manufactured by a Variable Single Beam e-Beam writer. Besides, we’ve explored the impact of mask quality on wafer imaging performance based on a clipped mask contour GDS and ILT model. Combined with simulation data on an ideal mask GDS and actual on wafer imaging data we able to separate mask impact on wafer imaging performance from other process fluctuations.
Inverse lithography technology (ILT) has been the focus of research for several years due to its ability to produce theoretically optimal mask shapes. However, its widespread adoption has been hindered by the complex computational techniques involved and the challenges associated with writing curvilinear ILT mask shapes. To enhance manufacturability, one approach involves streamlining the curvilinear mask shapes by converting them into simplified, ‘Manhattanized’ rectangular shapes using a mask rule constraint (MRC) compliant ILT method. The aim of this study is to examine the influence of mask fracture sizes on manufacturability and to assess the impact of traditional optical proximity correction (OPC), curvilinear ILT, and Manhattanized ILT on the quality of photographic images. The study focuses on challenging cell structures, and generating pattern shapes using traditional OPC, curvilinear ILT, and Manhattanized ILT with MRC compliance. Fracture sizes were varied from 5nm to 25nm in increments of 5nm. To compare mask manufacturability across different patterns, several factors were evaluated, including data fracturing, writing time, and metrology. Photographic image quality metrics, such as NILS (Normalized Image Log-Slope), MEEF (Mask Error Enhancement Factor), EPE (Edge Placement Error), PV-band (Process Variation Band), and CDOF (Common Depth of Focus) were also assessed. The comprehensive analysis aims to provide a better understanding of the trade-offs between different approaches and guide future improvements in mask manufacturability and image quality.
As chip feature sizes have continued to shrink, resolution enhancement techniques such as Optical Proximity Correction (OPC) have been utilized in advanced technology nodes. In recent years, Inverse Lithography Technology (ILT), a new OPC technique, has been widely applied in advanced Logic and Memory applications to improve imaging performance. Compared to the conventional OPC, ILT enables better process windows (PW) with low edge placement error (EPE) and high wafer critical dimension uniformity (CDU), etc. However, the nonrectilinear mask shapes in ILT make mask writing extremely complex and slow, which can potentially cause more mask manufacturing errors. Therefore, it’s important to quantitatively study the MEEF in ILT masks. In this work, we studied the MEEFs of 2D patterns corrected by ILT and conventional OPC and the differences between these two techniques. The results show that the MEEF at different positions (local MEEF) on an ILT mask has a bigger mean of ~3.14 and a smaller σ of ~0.09 relative to the mean of ~2.14 and σ of ~0.67 from a conventional OPC mask. The MEEF budget is analyzed based on the separated main features (MF) and subresolution assist features (SRAF). With SRAFs being inserted into the entire layout of the ILT mask, it contributes to all individual patterns with ~ 45% (1.49) of the total MEEF. Meanwhile, a conventional OPC mask only has SRAFs on the edges. Thus, SRAFs only contribute MEEF to the patterns located in the edge region (within the proximity effect range). Thus, the main center region of the OPC Mask has a lower MEEF contribution (~1.7). These results suggest that in the ILT recipe tuning process, MEEF should also be included in the cost function as a nonlinear factor so that the inversion can minimize MEEF while optimizing PW and EPE. Furthermore, the manhattanization of the ILT Mask can effectively reduce MEEF.
Mask corner rounding refers to the unintentional rounding deviation of sharp corners or edges during the mask making process, that is caused by the inherent limitations of the e-beam exposure system, such as beam blur, proximity effects, and the resist exposure process. It can have significant consequences on the lithography of chip manufacturing. This article compares the mask corner rounding behavior under different electron beam sizes and presents a novel Optical Proximity Correction (OPC) approach that incorporates mask corner rounding for various dimensional rectangular shapes, named Rounded Corner Aware OPC (RC-OPC). Contrasting with traditional OPC that rely on a single value for simulating mask corner rounding, this innovative OPC approach delivers substantial advantages including increased accuracy, exceptional lithographic performance, and better pattern fidelity, leading to a more dependable and robust process.
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