Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.
KEYWORDS: Design for manufacturing, Silicon, Polishing, Optical proximity correction, Back end of line, Metals, Failure analysis, Yield improvement, Logic, Manufacturing
A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic
process technologies. A noble technology combined a number of potential confliction of DFM techniques into a
comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon
diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are
optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and
advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve
manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented
in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5%
improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the
positive effect of the DFM techniques.
As the industry progresses toward smaller patterning nodes with tighter CD error budgets and narrower process
windows, the ability to control pattern quality becomes a critical, yield-limiting factor. In addition, as the feature size of
design layouts continues to decrease at 32nm and below, optical proximity correction (OPC) technology becomes more
complex and more difficult. From a lithographic point of view, it is the most important that the patterns are printed as
designed. However, unfavorable localized CD variation can be induced by the lithography process, which will cause
catastrophic patterning failures (i.e. ripple effects, and severe necking or bridging phenomenon) through process
variation. It is becoming even more severe with strong off-axis illumination conditions and other resolution enhancement
techniques (RETs). Traditionally, it can be reduced by optimizing the rule based edge fragmentation in the OPC setup,
but this fragmentation optimization is very dependent upon the engineer's skill. Most fragmentation is based on a set of
simple rules, but those rules may not always be robust in every possible design shape.
In this paper, a model based approach for solving these imaging distortions has been tested as opposed to a previous
rule based one. The model based approach is automatic correction techniques for reducing complexity of the OPC recipe.
This comes in the form of automatically adjusting fragments lengths along with feedback values at every OPC iterations
for a better convergence. The stability and coverage for this model based approach has been tested throughout various
layout cases.
If RET selection by simulation is to be successful for the deep sub-wavelength technologies
of today, then the predictions of the simulator must be quantitatively accurate over the parameter
space of interest. The Rigorous Physical resist Model (RPM) within PROLITH and Lithoware is
separable from the illumination conditions and the reflection behavior of the wafer stack, and thus
should be an excellent candidate for such projects.
In this work, the RPM is calibrated for a commercially available ArF photoresist using topdown
CD-SEM data, including focus-exposure matrices and CD vs. mask pitch data, under fixed
process conditions. It will be shown that this RPM is able to predict the performance of line, trench
and contact features, with quantitative accuracy, under different numerical aperture and illumination
conditions, even when the wafer stack is altered significantly. The stack alterations include resist
thickness change, the presence or absence of an immersion topcoat, substitution of different
underlying substrate materials and the use of a single or double layer anti-reflection coating. The
resist model accurately describes both the experimental calibration data and two separate
experimental validation datasets. The RMS error seen in the extrapolative predictions is comparable
to that observed between the model and the original calibration dataset.
The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to
meet the device performance and the process window latitude for the production level. The OPC model is generally
composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer
data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical
terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms
can deteriorate OPC stability in case of being overestimated by a small cost function.
Several physical terms have been used with ideal value in the optical property and even weren't be considered because
those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied
to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the
laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and
those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and
stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without
careful handling.
The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the
sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in
the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a
reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure
machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the
measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y
intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC
modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The
focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot
which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method.
Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source
and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into
the modeling.
With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device
node.
Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical
logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology
(RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced
optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the
distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are
observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a
LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification
of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test
block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the
OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should
go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography
technology nodes and upstream design for manufacturability (DFM) approaches.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.