Dr. Paul Hinnen Profile

Dr. Paul Hinnen

System Engineer at ASML Netherlands BV

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Author

Publications (25)

Proceedings Article | 26 May 2022 Presentation + Paper

On-product overlay solutions for DUV and EUV mix-scanner usage in an EPE-driven patterning world

D. Slotboom, P. Hinnen, J. Mulkens

Proceedings Volume 12051, 120510L (2022) https://doi.org/10.1117/12.2614537

KEYWORDS: Scanners, Overlay metrology, Semiconducting wafers, Distortion, Deep ultraviolet, Extreme ultraviolet, Reticles, Optical parametric oscillators

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Proceedings Article | 13 March 2018 Presentation + Paper

Holistic approach for overlay and edge placement error to meet the 5nm technology node requirements

Jan Mulkens, Bram Slachter, Michael Kubis, Wim Tel, Paul Hinnen, Mark Maslow, Harm Dillen, Eric Ma, Kevin Chou, Xuedong Liu, Weiming Ren, Xuerang Hu, Fei Wang, Kevin Liu

Proceedings Volume 10585, 105851L (2018) https://doi.org/10.1117/12.2297283

KEYWORDS: Metrology, Overlay metrology, Scanners, Semiconducting wafers, Extreme ultraviolet lithography, Logic, Optical proximity correction, Lithography, Critical dimension metrology, Electron beams

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Proceedings Article | 13 March 2018 Presentation + Paper

Unique method for controlling device level overlay with high-NA optical overlay technique using YieldStar in a DRAM HVM environment

Dong-Kiu Park, Hyun-Sok Kim, Moo-Young Seo, Jae-Wuk Ju, Young-Sik Kim, Mir Shahrjerdy, Arno van Leest, Aileen Soco, Giacomo Miceli, Jennifer Massier, Elliott McNamara, Paul Hinnen, Paul Böcker, Nang-Lyeom Oh, Sang-Hoon Jung, Yvon Chai, Jun-Hyung Lee

Proceedings Volume 10585, 105850V (2018) https://doi.org/10.1117/12.2297094

KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Control systems, Manufacturing, Etching, Lithography, Critical dimension metrology, Inspection

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Proceedings Article | 22 March 2016 Paper

Holistic, model-based optimization of edge leveling as an enabler for lithographic focus control: application to a memory use case

T. Hasan, Y.-S. Kang, Y.-J. Kim, S.-J. Park, S.-Y. Jang, K.-Y. Hu, E. J. Koop, P. C. Hinnen, M. M. A. Voncken

Proceedings Volume 9778, 97783G (2016) https://doi.org/10.1117/12.2219121

KEYWORDS: Semiconducting wafers, Scanners, Servomechanisms, Sensors, Optimization (mathematics), Lithography, Yield improvement, Model-based design, Control systems, Process control

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Proceedings Article | 19 March 2015 Paper

Intra-field patterning control using high-speed and small-target optical metrology of CD and focus

Hugo Cramer, Stefan Petra, Bastiaan Onne Fagginger Auer, Henk-Jan Smilde, Baukje Wisse, Steven Welch, Stefan Kruijswijk, Paul Hinnen, Bart Segers, Christian Leewis, Frank Staals, Maryana Escalante Marun, Stuart Young, Wei Guo, Arie den Boef

Proceedings Volume 9424, 94241F (2015) https://doi.org/10.1117/12.2085957

KEYWORDS: Semiconducting wafers, Metrology, Etching, Critical dimension metrology, Scanners, Scatterometry, Optical lithography, Optical metrology, Computer simulations, Overlay metrology

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Proceedings Article | 2 April 2014 Paper

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

Kai-Hsiung Chen, GT Huang, KS Chen, C. Hsieh, YC Chen, CM Ke, TS Gau, YC Ku, Kaustuve Bhattacharyya, Jacky Huang, Arie den Boef, Maurits v. d. Schaar, Martijn Maassen, Reinder Plug, Youping Zhang, Steffen Meyer, Martijn van Veen, Chris de Ruiter, Jon Wu, Hua Xu, Tatung Chow, Charlie Chen, Eric Verhoeven, Pu Li, Paul Hinnen, Greet Storms, Kelvin Pao, Gary Zhang, Christophe Fouquet, Takuya Mori

Proceedings Volume 9050, 90500S (2014) https://doi.org/10.1117/12.2047098

KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Back end of line, Scanners, Diffraction, Front end of line, Process control, Etching

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SPIE Journal Paper | 7 January 2014

Holistic optimization architecture enabling sub-14-nm projection lithography

Jan Mulkens, Paul Hinnen, Michael Kubis, Alexander Padiy, Jos Benschop

JM3, Vol. 13, Issue 01, 011006, (January 2014) https://doi.org/10.1117/12.10.1117/1.JMM.13.1.011006

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Lithography, Reticles, Metrology, Control systems, Projection lithography, Calibration, Actuators

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Proceedings Article | 12 April 2013 Paper

High order field-to-field corrections for imaging and overlay to achieve sub 20-nm lithography requirements

Jan Mulkens, Michael Kubis, Paul Hinnen, Roelof de Graaf, Hans van der Laan, Alexander Padiy, Boris Menchtchikov

Proceedings Volume 8683, 86831J (2013) https://doi.org/10.1117/12.2011550

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Metrology, Lithography, Actuators, Calibration, Reticles, Photomasks, Control systems

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Proceedings Article | 12 April 2013 Paper

Integrated scatterometry for tight overlay and CD control to enable 20-nm node wafer manufacturing.

Jos Benschop, Andre Engelen, Hugo Cramer, Michael Kubis, Paul Hinnen, Hans van der Laan, Kaustuve Bhattacharyya, Jan Mulkens

Proceedings Volume 8683, 86830P (2013) https://doi.org/10.1117/12.2011507

KEYWORDS: Overlay metrology, Metrology, Scanners, Sensors, Semiconducting wafers, Yield improvement, Signal processing, Scatterometry, Control systems, Wafer manufacturing

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Proceedings Article | 10 April 2013 Paper

CD optimization methodology for extending optical lithography

C. Wong, G. Seevaratnam, T. Wiltshire, N. Felix, T. Brunner, P. Rawat, M. Escalante, W. Kim, E. Rottenkolber, A. Elmalk, V. Wang, C. Leewis, P. Hinnen

Proceedings Volume 8681, 868137 (2013) https://doi.org/10.1117/12.2009397

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Scatterometry, Metrology, Photomasks, Etching, Scatter measurement, Scanning electron microscopy, Lithography, Semiconductors

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Proceedings Article | 13 March 2012 Paper

Driving imaging and overlay performance to the limits with advanced lithography optimization

Jan Mulkens, Jo Finders, Hans van der Laan, Paul Hinnen, Michael Kubis, Marcel Beems

Proceedings Volume 8326, 83261I (2012) https://doi.org/10.1117/12.916480

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Control systems, Metrology, Optical alignment, Reticles, Actuators, Calibration, Optimization (mathematics)

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Proceedings Article | 30 September 2011 Paper

3D features measurement using YieldStar: an angle resolved polarized scatterometer

Anne-Laure Charley, Philippe Leray, Koen D'havé, Shaunee Cheng, Paul Hinnen, Fahong Li, Peter Vanoppen, Mircea Dusa

Proceedings Volume 8169, 81690Q (2011) https://doi.org/10.1117/12.897582

KEYWORDS: 3D metrology, Scatterometry, Critical dimension metrology, Metrology, Lithography, 3D modeling, Optical proximity correction, Diffraction, Calibration, Scatter measurement

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Proceedings Article | 20 April 2011 Paper

3D features measurement using YieldStar, an angle resolved polarized scatterometer

Anne-Laure Charley, Philippe Leray, Koen D'havé, Shaunee Cheng, Paul Hinnen, Fahong Li, Peter Vanoppen, Mircea Dusa

Proceedings Volume 7971, 79712E (2011) https://doi.org/10.1117/12.881276

KEYWORDS: 3D metrology, Metrology, Critical dimension metrology, Lithography, Scatterometry, Scanning electron microscopy, Scatter measurement, 3D modeling, Optical proximity correction, Process control

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SPIE Journal Paper | 1 January 2011

New approaches for scatterometry-based metrology for critical distance and overlay measurement and process control

Kaustuve Bhattacharyya, Noelle Wright, Maurits van der Schaar, Arie den Boef, Paul Hinnen, Mir Shahrjerdy, Vivien Wang, Spencer Lin, Cathy Wang, Chih-Ming Ke, Jacky Huang, Willie Wang

JM3, Vol. 10, Issue 1, 013013, (January 2011) https://doi.org/10.1117/12.10.1117/1.3532076

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scanners, Critical dimension metrology, Birefringence, Distance measurement, Process control, Lithography, Scanning electron microscopy

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Proceedings Article | 2 April 2010 Paper

A single metrology tool solution for complete exposure tool setup

David Laidler, Koen D'havé, Anne-Laure Charley, Philippe Leray, Shaunee Cheng, Mircea Dusa, Peter Vanoppen, Paul Hinnen

Proceedings Volume 7638, 763809 (2010) https://doi.org/10.1117/12.848388

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Metrology, Calibration, Control systems, Scatterometry, Process control, Reticles, Diffraction

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Proceedings Article | 2 April 2010 Paper

Focus and dose deconvolution technique for improved CD control of immersion clusters

Anne-Laure Charley, Koen D'havé, Philippe Leray, David Laidler, Shaunee Cheng, Mircea Dusa, Paul Hinnen, Peter Vanoppen

Proceedings Volume 7638, 763808 (2010) https://doi.org/10.1117/12.848444

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Scanners, Data modeling, Scatterometry, Metrology, Lithography, Finite element methods, Reticles, Scatter measurement

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Proceedings Article | 14 December 2009 Paper

Improving 1D optical proximity effect matching for 45-nm node by scatterometry metrology

Dennis Chang, Reiner Jungblut, Jason Shieh, Alek Chen, Paul Hinnen, Henry Megens, Koen Schreel

Proceedings Volume 7520, 752036 (2009) https://doi.org/10.1117/12.849553

KEYWORDS: Scatterometry, Metrology, Scanners, Scanning electron microscopy, Optical proximity correction, Semiconducting wafers, Time metrology, Critical dimension metrology, Systems modeling, Lithography

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Proceedings Article | 5 April 2007 Paper

The application of SMASH alignment system for 65-55-nm logic devices

M. Miyasaka, H. Saito, T. Tamura, T. Uchiyama, Paul Hinnen, Hyun-Woo Lee, Marc van Kemenade, Mir Shahrjerdy, Robert van Leeuwen

Proceedings Volume 6518, 65180H (2007) https://doi.org/10.1117/12.711059

KEYWORDS: Optical alignment, Diffraction, Overlay metrology, Sensors, Signal processing, Semiconducting wafers, Optical design, Signal detection, Diffraction gratings, Manufacturing

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Proceedings Article | 5 April 2007 Paper

Advances in process overlay: alignment solutions for future technology nodes

Henry Megens, Richard van Haren, Sami Musa, Maya Doytcheva, Sanjay Lalbahadoersing, Marc van Kemenade, Hyun-Woo Lee, Paul Hinnen, Frank van Bilsen

Proceedings Volume 6518, 65181Z (2007) https://doi.org/10.1117/12.712149

KEYWORDS: Optical alignment, Semiconducting wafers, Overlay metrology, Photomasks, Metrology, Polarization, Refractive index, Signal detection, Semiconductors, Lithography

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Semiconductor industry has an increasing demand for improvement of the total lithographic overlay performance. To improve the level of on-product overlay control the number of alignment measurements increases. Since more mask levels will be integrated, more alignment marks need to be printed when using direct-alignment (also called layer-to-layer alignment). Accordingly, the alignment mark size needs to become smaller, to fit all marks into the scribelane. For an in-direct alignment scheme, e.g. a scheme that aligns to another layer than the layer to which overlay is being measured, the number of needed alignment marks can be reduced. Simultaneously there is a requirement to reduce the size of alignment mark sub-segmentations without compromising the alignment and overlay performance. Smaller features within alignment marks can prevent processing issues like erosion, dishing and contamination. However, when the sub-segmentation size within an alignment mark becomes comparable to the critical dimension, and thus smaller than the alignment-illuminating wavelength, polarization effects might start to occur. Polarization effects are a challenge for optical alignment systems to maintain mark detectability. Nevertheless, this paper shows how to actually utilize those effects in order to obtain enhanced alignment and overlay performance to support future technology nodes. Finally, another challenge to be met for new semiconductor product technologies is the ability to align through semi-opaque materials, like for instance new hard-mask materials. Enhancement of alignment signal strength can be reached by adapting to new alignment marks that generate a higher alignment signal. This paper provides a description of an integral alignment solution that meets with these emerging customer application requirements. Complying with these requirements will significantly enhance the flexibility in production strategies while maintaining or improving the alignment and overlay performance. This paper describes the methodology for optimization of the alignment strategy.

Proceedings Article | 26 March 2007 Paper

Integration of a new alignment sensor for advanced technology nodes

Paul Hinnen, Jerome Depre, Shinichi Tanaka, Ser-Yong Lim, Omar Brioso, Mir Shahrjerdy, Kazutaka Ishigo, Takuya Kono, Tatsuhiko Higashiki

Proceedings Volume 6520, 652023 (2007) https://doi.org/10.1117/12.712084

KEYWORDS: Optical alignment, Semiconducting wafers, Sensors, Overlay metrology, Manufacturing, Signal processing, Calibration, Lithography, Infrared sensors, Algorithm development

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In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

Proceedings Article | 12 May 2005 Paper

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

Scott Warrick, Paul Hinnen, Rob Morton, Kevin Cooper, Pierre-Olivier Sassoulas, Jerome Depre, Ramon Navarro, Richard van Haren, Clyde Browning, Doug Reber, Henry Megens

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.599807

KEYWORDS: Optical alignment, Semiconducting wafers, Chemical mechanical planarization, Copper, Scanning probe microscopy, Front end of line, Back end of line, Overlay metrology, Metals, Silicon

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Proceedings Article | 10 May 2005 Paper

Flexible alignment mark design applications using a next generation phase grating alignment system

Paul Hinnen, Hyun-Woo Lee, Stefan Keij, Hiroaki Takikawa, Keita Asanuma, Kazutaka Ishigo, Tatsuhiko Higashiki

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599494

KEYWORDS: Optical alignment, Semiconducting wafers, Sensors, Overlay metrology, Signal processing, Metrology, Optical design, Neodymium, Diffraction, Diffraction gratings

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Proceedings Article | 2 June 2003 Paper

Overlay performance with advanced ATHENA alignment strategies

Jeroen Huijbregste, Richard van Haren, Andre Jeunink, Paul Hinnen, Bart Swinnen, Ramon Navarro, Geert Simons, Frank van Bilsen, Hoite Tolsma, Henry Megens

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482814

KEYWORDS: Optical alignment, Semiconducting wafers, Aluminum, Overlay metrology, Chemical mechanical planarization, Spatial frequencies, Signal processing, Copper, Scanning probe microscopy, Sensors

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Proceedings Article | 30 July 2002 Paper

Integration of new alignment mark designs in dual inlaid-copper interconnect processes

Scott Warrick, Paul Hinnen, Richard van Haren, Chris Smith, Henry Megens, Chong-Cheng Fu

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474476

KEYWORDS: Optical alignment, Semiconducting wafers, Overlay metrology, Copper, Dielectrics, Scanning probe microscopy, Signal processing, Reflectivity, Polishing, Metals

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Proceedings Article | 22 August 2001 Paper

Advances in process overlay

Paul Hinnen, Henry Megens, Maurits van der Schaar, Richard van Haren, Evert Mos, Sanjay Lalbahadoersing, Frank Bornebroek, David Laidler

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436734

KEYWORDS: Semiconducting wafers, Optical alignment, Copper, Overlay metrology, Metals, Metrology, Silicon, Aluminum, Chemical mechanical planarization, Polishing

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Showing 5 of 25 publications

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