Editor-in-Chief Harry Levinson addresses the importance of maintaining a professional attitude in scientific peer reviews.

Editor-in-Chief Harry Levinson introduces a new set of guidelines for papers related to computational lithography.

Editor-in-Chief Harry Levinson outlines new guidelines for semiconductor plasma-etch technology.

Guest Editor Linhong (Leo) Pang summarizes the Special Section on Deep Learning for Lithography and Photomask Applications.

Background: Thin mask model has been conventionally used in optical lithography simulation. In extreme ultraviolet (EUV) lithography thin mask model is not valid because the absorber thickness is comparable to the mask pattern size. Rigorous electromagnetic (EM) simulations have been used to calculate the thick mask amplitudes. However, these simulations are highly time consuming.

Aim: Proposing a prototype of a convolutional neural network (CNN) which reduces the calculation time of rigorous EM simulations in a small mask area with specific mask patterns.

Approach: We construct a CNN which reproduces the results of the EM simulation. We define mask 3D amplitude as the difference between the thick mask amplitude and the thin mask amplitude. The mask 3D amplitude of each diffraction order is approximated using three parameters which represent the on-axis and the off-axis mask 3D effects. The mask 3D parameters of all diffraction orders are trained by a CNN.

Results: The input and the targets of the CNN are a cut-mask pattern and mask 3D parameters calculated by the EM simulation, respectively. After the training with 199,900 random cut-mask patterns, the CNN successfully predicts the mask 3D parameters of new cut-mask patterns.

Conclusions: We construct a CNN which predicts the diffraction amplitudes from 2D EUV mask patterns. After the training, the CNN successfully reproduces the mask 3D amplitude. CNN prediction is 5000 times faster than the rigorous EM simulation. Next challenge is to construct a practical CNN which covers a large area with general mask patterns.

Background: Finding optimal processing conditions to reduce defectivity is a major challenge in high-resolution lithographic tools such as directed self-assembly and extreme ultraviolet lithography.

Aim: We aim to develop an efficient automated method that can detect defects and identify their types and locations, allowing for assessing the performance of lithographic processing conditions more easily.

Approach: We propose a deep learning approach using an object recognition neural network for the classification and detection of defects in scanning electron microscopy (SEM) images featuring line-space patterns. We optimized our network by exploring its design variables and applied it on a case with limited numbers of SEM images available for training the network.

Results: With an optimized network and data augmentation strategies (flipping and mixing images from simulations), it was possible to achieve a significant increase in the performance of the network. Transferability of the network was also proven when applied on a more diverse dataset of SEM images gathered from selected publications.

Conclusions: The outcome of our work shows that the amalgamation of an optimal network design and augmentation strategies performs satisfactorily for defectivity analysis and is generic for data not constrained to fixed settings.

Background: E-beam metrologies, both critical dimension scanning electron microscope metrology and defect scan metrology, have been playing a very critical role in gating patterning quality. SEM images can provide rich visual information for engineers to do qualitative and quantitative analyses. However, the low e-beam metrology tool throughput makes it impossible to obtain SEM images for larger area. Monte Carlo-based SEM image simulations or other SEM image simulations require postlithography or postetch pattern three-dimensional structures as prerequisite, and the simulation speed is not sufficiently fast for full chip implementation.

Aim: We aim to develop machine learning SEM models with sufficient accuracy and speed for full chip application in semiconductor manufacturing environment.

Approach: We have proposed a virtual SEM metrology solution based on U-Net neural network with physics-based feature maps as model input. With information in aerial image space encoded properly, SEM images of both postlithography and postetch can be predicted accurately enough for practical applications using our proposed virtual SEM metrology models. Equipped with GPUs, the machine learning-based SEM image models are fast enough to make it possible to realize full chip SEM generation from post-OPC data.

Results: Our machine learning SEM image models can predict SEM images with normalized cross correlation around 0.95 in reference to ground truth SEM images, each SEM image (512  ×  512 in size) takes about 800 ms using single CPU, and the speed can be accelerated to about 10 ms with single GPU.

Conclusions: Using U-Net structure and physics-based feature maps as model inputs, machine learning-based SEM image models can be developed. The models are sufficiently accurate and fast to find their applications in semiconductor manufacturing, and they can be used as independent model for OPC data verification or generate SEM images as reference for SEM defect scan metrology.

Background: Deep learning is a very fast-growing field in the area of artificial intelligence with remarkable results in recent years. Many works in the lithography and photomask field have shown progress of technology in this application area and the potential to improve lithography by the automation of processes. Despite this progress, the use of machine learning techniques in the field of mask repair still seems to be at the beginning.

Aim: We show that deep learning-based methods can successfully be applied to mask repair applications.

Approach: The presented system is a hybrid and modular approach based on a combination of several deep learning networks and analytical methods, enabling the detection of mask pattern defects and the determination of the exact defect shapes from SEM images. In the current version, the system is trained for line/space patterns and contact patterns with typical defect types. The modularity allows for the extensibility to new use cases. The issue of an insufficient amount of training data is addressed using purely computer-generated simplified SEM data in combination with a specific network architecture.

Results: The very good functionality and defect detection accuracy of the system are demonstrated with a set of real SEM images with line/space patterns and contact patterns with numerous defects. In particular, a 100% true defect detection rate could be obtained.

Conclusions: The presented machine learning approach demonstrates the successful defect identification, location, and shape determination from real mask SEM images.

Background: Machine learning is predicted to have an increasingly important role in semiconductor metrology. Prediction intervals that describe the reliability of the predictive performance of machine learning models are important to guide decision making and to improve trust in deep learning and other forms of machine learning and artificial intelligence. Image processing is an important application of artificial intelligence. Low-dose images from the scanning electron microscope (SEM) are often used for roughness measurements such as line edge roughness (LER) because of relatively small acquisition times and resist shrinkage, but such images are corrupted by noise, blur, edge effects, and other instrument errors. LER affects semiconductor device performance and the yield of the manufacturing process.

Aim: We consider prediction intervals for the deep convolutional neural network EDGENet, which was trained on a large dataset of simulated SEM images and directly estimates the edge positions from a SEM rough line image containing an unknown level of Poisson noise.

Approach: Conformal prediction is a relatively recent, increasingly popular, rigorously proven, and simple methodology to address this need for both classification and regression problems, and it does not use distributional assumptions such as Gaussianity or the Bayesian framework; one new variant combines it with another technique to generate prediction intervals known as quantile regression.

Results: We illustrate the strengths and limitations of different conformal prediction procedures for the EDGENet approach to LER estimation. Combining these approaches into ensemble schemes and incorporating domain knowledge produces more informative prediction intervals.

Conclusions: Deep learning models can help in the estimation of LER, but their acceptance has been hindered by a lack of trust in these techniques. Prediction intervals that provide coverage guarantees are an approach to alleviate this problem and may catalyze the transition within semiconductor manufacturing to a wider acceptance and implementation of machine learning.

The mask 3D effect is important even for deep ultraviolet lithography. After the wavelength becomes shorter in extreme ultraviolet (EUV) regime, it becomes even more important. We also need to consider the asymmetric effect as well as the shadow effects now. To model these effects correctly, it is critical to compute the electromagnetic near field around the EUV absorbers correctly. Though FDTD, FEM, and RCWA methods have been applied to do so, we are here trying to combine the FEM method with deep learning techniques to achieve a better computational competence in the speed and accuracy. We only compute the one-dimensional (1D) situation with TE type incident wave. With parts of the near field signal just below the absorber computed by the FEM method, 1D patch generative adversarial network (GAN) technique is used to learn the paired mapping between the distribution of the near field below the absorber and the geometry of the mask absorber. The scattering model of the EUV absorbers obtained this way can be combined with the reflector model afterward to form the whole EUV mask model.

Hotspot detection focused on lithography induced defects becomes crucial at advanced node due to the increasing complexity of the design and manufacture process. Compared with traditional lithography simulation techniques for hotspot detection, machine-learning-based methods have shown significant advantages attributing to the efficiency and generality of their model. However, most convolutional neural network-based hotspot detector can only inference a layout pattern at once. Therefore, sampling clip patterns from the detected layout is the bottleneck of the whole process and determines the performance of hotspot detection. We designed a flow to generate filter rules by clustering analysis of known hotspots, which can efficiently extract layout clips as detected samples to hotspot classifier. We further propose a feature parametric optimization method to extract valuable graphic features for classifiers and reduce redundancy from context patterns. Experimental results demonstrate that these techniques improve the accuracy of hotspots detection.

Background: As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have since been widely adopted.

Aim: The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better PW as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion.

Approach: Generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix, and CycleGAN, were first trained and then utilized to synthesize realistic ILT images.

Results: These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon source-mask optimizer (SMO).

Conclusions: Methodologies of SRAF placement based on GANs were demonstrated in this paper. While traditional MO approach showed the best lithography performance, CycleGAN in particular was close behind and had much better performance than conventional RB-SRAF approach, whilst achieving good stability for different layout environments. Most importantly, the efficiency of SRAF insertion can be enhanced significantly through GANs.

Guest Editors Alan Brodie and Martha I. Sanchez introduce the JM3 Special Section on Masks and Lithography in the Era of Multi-beam Mask Writers.

Background: EUV lithography is making substantial progress in optimizing (i) tool, (ii) mask blanks, and (iii) resist materials to support the next generation EUV imaging performance. EUV masks use a variety of absorbers and capping layers fabricated on mirroring multi-layer (ML) stacks.

Aim: The highly conformal e-beam resist-patterning process needs to understand the absorbed intensity distribution spread from the electron scattering in the resist/substrate stack, as well as the consecutive radiation-chemical effects induced by the electron energy spread together with the dissolution behavior of the resist.

Approach: We present the results of resist response to 50-keV electron multi-beam exposure based on statistical numerical simulation on different EUV absorbers and reflecting ML stacks directly compared with the numerical lithographic parameters extracted from the experimental resist screening. The experiments were performed with the IMS Nanofabrication Multi-Beam Mask Writer (MBMW) ALPHA tool in a positive Chemically Amplified Resist provided by FUJIFILM, coated on experimental EUV masks with different stack compositions prepared by HOYA.

Results: All input parameters for MBMW corrections were precisely specified to the corresponding absorbed energy distribution signature of the specific EUV stack. Experiments confirmed the necessity to match the model calibration values to each small change in the mask stack composition.

Conclusions: The method was successfully implemented into leading-edge mask writing and resist/substrate/tool testing for achieving the sub-7-nm node at different EUV-mask stacks.

Inverse lithography technology (ILT) optical proximity correction is going to play a critical role in addressing challenges of optical and EUV lithography as the industry pushes toward advanced nodes. One major barrier in adoption of ILT has been the mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multibeam mask writers, this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting newer formats that already reduce file size. However, as the ILT shape complexity and data volume increases further for 5 nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look toward other compact formats of data representation that will be capable of serving well for multiple generations of mask making. We compare various curvilinear data representation schemes and their value in the curvilinear ILT-based mask manufacturing flow. We demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows. The same format may not be applicable for all types of features in the input mask. These options will be discussed. We will compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods and discuss the extents and limits of all these techniques. To evaluate practical use of curvilinear representation in place of conventional piecewise linear representation, we manufacture and measure a photomask to evaluate the accuracy of curvilinear representations. Finally, we use EUV AIMS to assess the impact of curvilinear representation on wafer process window.

NuFlare Technology, Inc. has developed the charge effect correction (CEC) system, in which the predicted placement errors caused by resist surface charge effect are compensated. Due to good reproducibility of these exposure-dose-dependent and time-dependent behaviors, CEC has successfully improved image placement accuracy in single variable-shaped electron beam mask (EBM) writers. The physical mechanism of resist charging, however, has remained unclear. Considering large difference in beam current densities between EBM and multi-beam mask writers (MBM), it is concerning that unexpected charge phenomena occur. Therefore, it is required to reveal the mechanism and to show the resist charging is still predictable in MBM by a common charging model. In order to provide validity of CEC consistently with EBM and MBM, the surface charge densities caused in EBM writers and MBM-2000 were experimentally evaluated from those placement errors. The charge densities strongly depend on the resist thickness meanwhile they do not change significantly by the writers. Furthermore, equations to reproduce those experimental results are proposed in terms of a physical model, which takes into account low-energy secondary electrons drawn to resist surface by an already-existing surface charge and vertical flow of the charge in the resist.

Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today’s advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical “hotspots” on chips, but had not been used for entire chips.

Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops.

Approach: The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement—partitioning and stitching—has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time.

Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies—a doubling in the wafer process window—for semiconductor manufacturing.

Background: As extreme ultraviolet lithography (EUV) lithography has progressed toward feature dimensions smaller than the wavelength, electromagnetic field (EMF) solvers have become indispensable for EUV simulations. Although numerous approximations such as the Kirchhoff method and compact mask models exist, computationally heavy EMF simulations have been largely the sole viable method of accurately representing the process variations dictated by mask topography effects in EUV lithography.

Aim: Accurately modeling EUV lithographic imaging using deep learning while taking into account 3D mask effects and EUV process variations, to surpass the computational bottleneck posed by EMF simulations.

Approach: Train an efficient generative network model on 2D and 3D model aerial images of a variety of mask layouts in a manner that highlights the discrepancies and non-linearities caused by the mask topography.

Results: The trained model is capable of predicting 3D mask model aerial images from a given 2D model aerial image for varied mask layout patterns. Moreover, the model accurately predicts the EUV process variations as dictated by the mask topography effects.

Conclusions: The utilization of such deep learning frameworks to supplement or ultimately substitute rigorous EMF simulations unlocks possibilities of more efficient process optimizations and advancements in EUV lithography.

Background: X-ray grating interferometry is an emerging imaging technique that strongly relies on fine grating structures. A common method to fabricate compatible gratings is deep x-ray lithography (DXRL).

Aim: To develop a method to fabricate grating structures by DXRL, which does not require a synchrotron source.

Approach: The synchrotron source is replaced by a conventional x-ray tube. The fabrication process is adapted for the divergent beam by cylindrically bending mask and substrate.

Results: A 10-μm period absorption grating with 80-μm-thick gold lamellae is successfully fabricated from an intermediate 110-μm high structured resist. This grating is characterized and implemented in a preclinical Talbot-Lau interferometer designed for medical thorax imaging.

Conclusion: This approach can overcome the strong dependence on synchrotron facilities for the fabrication of gratings for x-ray grating interferometry. As x-ray tubes are more widely available, this is a cost-efficient and scalable alternative suitable for industrial production.

Background: Systematic/stochastic pattern defects affect the production yield of integrated circuits (IC) containing trillions of 10-nm level features.

Aim: We detect pattern anomalies/defects from images obtained from scanning electron microscopes (SEM) for random/arbitrary IC patterns without using design data.

Approach: We decompose SEM images into small sub-images and apply an identical autoencoder to each of them to detect anomalies. The astronomical varieties in random IC patterns are reduced into limited varieties in elementary patterns, which are coded onto limited dimension latent vectors in autoencoder. The discrepancy between autoencoder input and output represents a deviation of local pattern shapes from ideal or allowed ones and is used as an index of anomaly.

Results: A wide variety of anomalies/defects are detected in regular and random IC patterns fabricated by extreme ultra-violet lithography without prior knowledge about anomalies at a high signal-to-noise ratio within a time shorter than the typical image acquisition time of SEMs. They include missing/necking in holes/trenches, collapsing/breaking in lines, various local pattern distortion/deformation, and tiny particles. Frequency and spatial distributions of the discrepancy index are sensitive to process changes and can be used for visualizing the sign or causes of anomalies.

Conclusions: The method is effective for inspecting memory and random logic ICs with high-speed SEMs.

Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future.

Aim: The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years.

Results: Critical dimensions in logic chips are now small enough that stochastics, i.e., random variations in photon, molecules, and photoresist image forming processes, introduces random variations in sizes and stochastic-driven defects. As critical dimensions get smaller, stochastics becomes a bigger challenge. The roadmap projects that despite projected improvements in tools, photoresist, device design, and patterning processes, resist dose to print will still have to roughly triple over the next 10 years to maintain acceptable stochastics unless major process or chip design changes are made. This will raise patterning costs substantially. Other patterning options are under development but they also have challenges related to defects. Edge placement error (EPE) is also a challenge for future devices. Long-term, logic device requirements will drive stacked devices, and yield and process complexity will be key challenges.

Conclusions: Logic devices will drive leading edge lithography. Improved extreme ultraviolet lithography is a leading candidate but other options are possible. Key short-term challenges are stochastics, EPE, and cost. Resist dose to print is expected to rise substantially as critical dimensions shrink unless substantial process innovation occurs. For the long term, the challenges will be yield and process complexity when logic devices switch to 3D scaling